Message-ID: <CA+kK7ZhaqWrEkRzGrOtLwbs1fiyXAeztKy9P6-LgJx_GAWevtw@mail.gmail.com>
Date:   Sat, 19 Jun 2021 12:38:44 -0400
From:   Jon Masters <jcm@...hat.com>
To:     Jason Gunthorpe <jgg@...dia.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Will Deacon <will@...nel.org>,
        Vikram Sethi <vsethi@...dia.com>,
        Vidya Sagar <vidyas@...dia.com>,
        Thierry Reding <treding@...dia.com>,
        Jon Masters <jcm@...masters.org>,
        Jeremy Linton <jeremy.linton@....com>,
        Mark Rutland <mark.rutland@....com>, linux-pci@...r.kernel.org,
        Sudeep Holla <sudeep.holla@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-arm-kernel@...ts.infradead.org,
        Eric Brower <ebrower@...dia.com>, Grant.Likely@....com
Subject: Re: [PATCH] arm64: PCI: Enable SMC conduit

P.S. Note that you shouldn't have to do any of the below because this
is exactly what someone should be sitting on Cadence and Synopsys for
until they do it correctly in licenseable IP that just does the right
thing. A real RC as a unit. No more root ports and vendors having to
hack it together. If we want to solve the actual problem, then that is
the actual problem.

Ok, off my hobby horse ;)

On Sat, Jun 19, 2021 at 12:34 PM Jon Masters <jcm@...hat.com> wrote:
>
> Hi Jason,
>
> On Fri, Jun 18, 2021 at 10:06 AM Jason Gunthorpe <jgg@...dia.com> wrote:
> >
> > On Fri, Jun 18, 2021 at 09:21:54AM -0400, Jon Masters wrote:
> > >    Hi Jason,
> > >    On Wed, Jun 16, 2021 at 1:38 PM Jason Gunthorpe <[1]jgg@...dia.com>
> > >    wrote:
> > >
> > >      On Thu, Mar 25, 2021 at 01:12:31PM +0000, Lorenzo Pieralisi wrote:
> > >      However, in modern server type systems the PCI config space is often
> > >      a
> > >      software fiction being created by firmware throughout the PCI
> > >      space. This has become necessary as the config space has exploded in
> > >      size and complexity and PCI devices themselves have become very,
> > >      very
> > >      complicated. Not just the config space of single devices, but even
> > >      bridges and topology are SW created in some cases.
> > >      HW that is doing this is already trapping the config cycles somehow,
> > >      presumably with some very ugly way like x86's SMM. Allowing a
> > >      designed
> > >      in way to inject software into the config space cycles does sound a
> > >      lot cleaner and better to me.
> > >
> > >    This is not required. SMM is terrible, indeed. But we don't have to
> > >    relive it in Arm just because that's [EL3] the easy place to shove
> > >    things :)
> >
> > "This is not required"? What does that mean?
>
> It's not required to implement platform hacks in SMM-like EL3. The
> correct place to do this kind of thing is behind the scenes in a
> platform microcontroller (note that I do not necessarily mean Arm's
> SCP approach, you can do much better than that).
>
> > >      For instance it may solve other pain points if ARM systems had a
> > >      cheap
> > >      way to emulate up a "PCI device" to wrapper around some IP blob on
> > >      chip. The x86 world has really driven this approach where everything
> > >      on SOC is PCI discoverable, and it does seem to work well.
> > >      IMHO SW emulation of config space is an important ingredient to do
> > >      this.
> > >
> > >    There are certainly ways to build PCI configuration space in a
> > >    programmable way that does not require software trapping into
> > >    MM.
> >
> > Can you elaborate on what you'd like to see here? Where do you want to
> > put the software then?
>
> There are places other than EL3 where this should live. It should not
> involve the AP at all in a correct configuration. It should (only)
> appear to be done in hardware, but where you do it is up to an
> implementation. Doing it correctly also accounts for others accessing
> configuration space simultaneously. You don't want to have to stop the
> world, or break PCI ordering semantics on access. There is a right way
> (hardware) to do this, and a wrong way (EL3 hacks). But I'll leave
> folks to figure out how to implement it. There are several possible
> approaches to do this.
>
> > >    I strongly agree with the value of an industry standard approach
> > >    to this in hardware, particularly if the PCIe vendors would offer
> > >    this as IP.  In a perfect world, ECAM would simply be an
> > >    abstraction and never directly map to fixed hardware, thus one
> > >    could correct defects in behavior in the field. I believe on the
> > >    x86 side of the house, there is some interesting trapping support
> > >    in the LPC/IOH already and this is absolutely what Arm should be
> > >    doing.
> >
> > AFAIK x86 has HW that traps the read/writes to the ECAM and can
> > trigger a FW flow to emulate them, maybe in SMM, I don't know the
> > details. It ceratinly used to be like this when SMM could trap the
> > config space io read/write registers.
>
> They trap to something that isn't in SMM, but it is in firmware. That
> is the correct (in my opinion) approach to this. It's one time where
> I'm going to say that all the Arm vendors should be doing what Intel
> is doing in their implementation today.
>
> > Is that what you want to see for ARM? Is that better than a SMC?
>
> Yes, because you preserve perfect ECAM semantics and correct it behind
> the scenes. That's what people should be building.
>
> > That is alot of special magic hardware to avoid a SMC call...
>
> And it's the correct way to do it. Either that, or get ECAM perfect up
> front and do pre-si testing under emulation to confirm.
>
> </opinion>
>
> Jon.

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