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Message-ID: <CANAwSgRi7UcS22QKZRRhwYvB3Dyk0ChowX+KByEsxP35ezjtKw@mail.gmail.com>
Date: Mon, 21 Jun 2021 12:45:00 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Neil Armstrong <narmstrong@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
linux-phy@...ts.infradead.org,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-amlogic@...ts.infradead.org,
Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFCv1 7/8] phy: amlogic: meson8b-usb2: Power off the PHY by
putting it into reset mode.
Hi Martin,
On Fri, 18 Jun 2021 at 04:07, Martin Blumenstingl
<martin.blumenstingl@...glemail.com> wrote:
>
> Hi Anand,
>
> On Thu, Jun 17, 2021 at 9:44 PM Anand Moon <linux.amoon@...il.com> wrote:
> [...]
> > @@ -245,8 +250,6 @@ static int phy_meson8b_usb2_power_on(struct phy *phy)
> > regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_FSEL_MASK,
> > 0x5 << REG_CTRL_FSEL_SHIFT);
> > /* reset the PHY */
> > - regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET,
> > - REG_CTRL_POWER_ON_RESET);
> The vendor driver uses the following sequence for the power on reset:
> - set the power on reset bit
> - wait 500us
> - clear the power on reset bit
> - wait 500us
>
> With your change we now:
> - wait 500us
> - clear the power on reset bit
> - wait 500us
>
> I don't know if this is sufficient to bring the PHY into a well-defined state.
> Maybe it works, maybe it doesn't reset at all in this case - I don't
> know how to verify this though.
>
Initially, I tried to some bit mask code to resolve this but it failed,
So no harm in keeping the original changes.
There is another parameter REG_CTRL_PORT_RESET to be considered.
>
> Best regards,
> Martin
Thanks
-Anand
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