linux-kernel - Re: [PATCH 2/4] MIPS: Loongson64: Add GMAC support for Loongson-2K1000

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YNAAo+ABaMVmArcM@lunn.ch>
Date:   Mon, 21 Jun 2021 04:59:47 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Qing Zhang <zhangqing@...ngson.cn>
Cc:     Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Rob Herring <robh+dt@...nel.org>,
        Huacai Chen <chenhc@...ote.com>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        netdev@...r.kernel.org
Subject: Re: [PATCH 2/4] MIPS: Loongson64: Add GMAC support for
 Loongson-2K1000

> +			gmac@3,1 {
> +				compatible = "pci0014,7a03.0",
> +						   "pci0014,7a03",
> +						   "pciclass0c0320",
> +						   "pciclass0c03",
> +						   "loongson, pci-gmac";
> +
> +				reg = <0x1900 0x0 0x0 0x0 0x0>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
> +					     <15 IRQ_TYPE_LEVEL_LOW>;
> +				interrupt-names = "macirq", "eth_lpi";
> +				interrupt-parent = <&liointc0>;
> +				phy-mode = "rgmii";

rgmii? But you set PHY_INTERFACE_MODE_GMII?

> +				mdio {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					compatible = "snps,dwmac-mdio";
> +					phy1: ethernet-phy@1 {
> +						reg = <0>;

The value after the @ should match the reg value.

    Andrew