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Message-Id: <20210622102907.99242-1-heiko@sntech.de>
Date: Tue, 22 Jun 2021 12:29:06 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: cl@...k-chips.com
Cc: heiko@...ech.de, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
kever.yang@...k-chips.com
Subject: [PATCH 09/10] arm64: dts: rockchip: add pwm nodes for rk3568
From: Liang Chen <cl@...k-chips.com>
Add the pwm controller nodes to the core rk3568 dtsi.
Signed-off-by: Liang Chen <cl@...k-chips.com>
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 176 +++++++++++++++++++++++
1 file changed, 176 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d225e6a45d5c..33db226b46cb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -257,6 +257,50 @@ uart0: serial@...50000 {
status = "disabled";
};
+ pwm0: pwm@...70000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70000 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm0m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@...70010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70010 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm1m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@...70020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70020 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm2m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@...70030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfdd70030 0x0 0x10>;
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
sdmmc2: mmc@...00000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
@@ -525,6 +569,138 @@ uart9: serial@...d0000 {
status = "disabled";
};
+ pwm4: pwm@...e0000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm4_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@...e0010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@...e0020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm6_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@...e0030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6e0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm7_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm8: pwm@...f0000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm8m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@...f0010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm9m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm10: pwm@...f0020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm10m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm11: pwm@...f0030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe6f0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm11m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm12: pwm@...00000 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700000 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm12m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm13: pwm@...00010 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700010 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm13m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm14: pwm@...00020 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700020 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm14m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm15: pwm@...00030 {
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfe700030 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm15m0_pins>;
+ pinctrl-names = "active";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
--
2.29.2
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