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Message-Id: <20210623192002.3671647-12-yazen.ghannam@amd.com>
Date: Wed, 23 Jun 2021 19:19:42 +0000
From: Yazen Ghannam <yazen.ghannam@....com>
To: linux-edac@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, mchehab@...nel.org,
tony.luck@...el.com, Smita.KoralahalliChannabasappa@....com,
Yazen Ghannam <yazen.ghannam@....com>
Subject: [PATCH v2 11/31] EDAC/amd64: Define function to add DRAM base and hole
Move adding of DRAM base and hole into a separate helper function.
Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
---
Link:
https://lkml.kernel.org/r/20210507190140.18854-8-Yazen.Ghannam@amd.com
v1->v2:
* Moved from arch/x86 to EDAC.
drivers/edac/amd64_edac.c | 45 ++++++++++++++++++++++-----------------
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ebb82b5e155b..68c4aecd5e7a 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1320,14 +1320,34 @@ static int denormalize_addr(struct addr_ctx *ctx)
return 0;
}
-static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
+static int add_base_and_hole(struct addr_ctx *ctx)
{
- u64 dram_base_addr, dram_limit_addr, dram_hole_base;
+ u64 dram_base_addr = (ctx->reg_base_addr & GENMASK_ULL(31, 12)) << 16;
- u32 tmp;
+ /* Add dram base address */
+ ctx->ret_addr += dram_base_addr;
+
+ /* If legacy MMIO hole enabled */
+ if (ctx->reg_base_addr & BIT(1)) {
+ u32 dram_hole_base;
+
+ if (amd_df_indirect_read(0, df_regs[DRAM_HOLE_CTL],
+ DF_BROADCAST, &dram_hole_base))
+ return -EINVAL;
+
+ dram_hole_base &= GENMASK(31, 24);
+ if (ctx->ret_addr >= dram_hole_base)
+ ctx->ret_addr += (BIT_ULL(32) - dram_hole_base);
+ }
+
+ return 0;
+}
+
+static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
+{
+ u64 dram_limit_addr;
u8 hashed_bit;
- u8 lgcy_mmio_hole_en;
struct addr_ctx ctx;
@@ -1354,23 +1374,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
if (denormalize_addr(&ctx))
goto out_err;
- lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1);
- dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16;
-
dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
- /* Add dram base address */
- ctx.ret_addr += dram_base_addr;
-
- /* If legacy MMIO hole enabled */
- if (lgcy_mmio_hole_en) {
- if (amd_df_indirect_read(nid, df_regs[DRAM_HOLE_CTL], umc, &tmp))
- goto out_err;
-
- dram_hole_base = tmp & GENMASK(31, 24);
- if (ctx.ret_addr >= dram_hole_base)
- ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
- }
+ if (add_base_and_hole(&ctx))
+ goto out_err;
if (ctx.hash_enabled) {
/* Save some parentheses and grab ls-bit at the end. */
--
2.25.1
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