linux-kernel - Re: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs

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Message-ID: <1431023086.718458.1624430227963@mail1.libero.it>
Date:   Wed, 23 Jun 2021 08:37:07 +0200 (CEST)
From:   Dario Binacchi <dariobin@...ero.it>
To:     Gabriel FERNANDEZ <gabriel.fernandez@...com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Cc:     Alexandre TORGUE - foss <alexandre.torgue@...s.st.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-stm32@...md-mailman.stormreply.com" 
        <linux-stm32@...md-mailman.stormreply.com>,
        Gabriel FERNANDEZ - foss <gabriel.fernandez@...s.st.com>
Subject: Re: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs

Hi Gabriel,

> Il 23/06/2021 08:27 Gabriel FERNANDEZ <gabriel.fernandez@...com> ha scritto:
> 
>  
> Hi Dario,
> 
> I agree with your analyse. 
> You have to change also 'u8 pll_num' from 'stm32f4_pll_post_div_data' structure into 'int pll_idx' 
> or something like that.

Always in the same patch or in a different one?

Thanks and regards,
Dario

> Many Thanks !
> Gabriel
> 
> 
> From: Dario Binacchi <dariobin@...ero.it>
> Sent: Tuesday, June 22, 2021 11:14 PM
> To: linux-clk@...r.kernel.org <linux-clk@...r.kernel.org>
> Cc: Dario Binacchi <dariobin@...ero.it>; Alexandre TORGUE - foss <alexandre.torgue@...s.st.com>; Gabriel FERNANDEZ <gabriel.fernandez@...com>; Maxime Coquelin <mcoquelin.stm32@...il.com>; Michael Turquette <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; linux-arm-kernel@...ts.infradead.org <linux-arm-kernel@...ts.infradead.org>; linux-kernel@...r.kernel.org <linux-kernel@...r.kernel.org>; linux-stm32@...md-mailman.stormreply.com <linux-stm32@...md-mailman.stormreply.com>
> Subject: [PATCH] clk: stm32f4: fix post divisor setup for I2S/SAI PLLs 
>  
> Enabling the framebuffer leads to a system hang. Running, as a debug
> hack, the store_pan() function in drivers/video/fbdev/core/fbsysfs.c
> without taking the console_lock, allows to see the crash backtrace on
> the serial line.
> 
> ~ # echo 0 0 > /sys/class/graphics/fb0/pan
> 
> [    9.719414] Unhandled exception: IPSR = 00000005 LR = fffffff1
> [    9.726937] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9
> [    9.733008] Hardware name: STM32 (Device Tree Support)
> [    9.738296] PC is at clk_gate_is_enabled+0x0/0x28
> [    9.743426] LR is at stm32f4_pll_div_set_rate+0xf/0x38
> [    9.748857] pc : [<0011e4be>]    lr : [<0011f9e3>]    psr: 0100000b
> [    9.755373] sp : 00bc7be0  ip : 00000000  fp : 001f3ac4
> [    9.760812] r10: 002610d0  r9 : 01efe920  r8 : 00540560
> [    9.766269] r7 : 02e7ddb0  r6 : 0173eed8  r5 : 00000000  r4 : 004027c0
> [    9.773081] r3 : 0011e4bf  r2 : 02e7ddb0  r1 : 0173eed8  r0 : 1d3267b8
> [    9.779911] xPSR: 0100000b
> [    9.782719] CPU: 0 PID: 49 Comm: sh Not tainted 5.13.0-rc5 #9
> [    9.788791] Hardware name: STM32 (Device Tree Support)
> [    9.794120] [<0000afa1>] (unwind_backtrace) from [<0000a33f>] (show_stack+0xb/0xc)
> [    9.802421] [<0000a33f>] (show_stack) from [<0000a8df>] (__invalid_entry+0x4b/0x4c)
> 
> The `pll_num' field in the post_div_data configuration contained a wrong
> value which also referenced an uninitialized hardware clock when
> clk_register_pll_div() was called.
> 
> Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> Signed-off-by: Dario Binacchi <dariobin@...ero.it>
> 
> ---
> 
>  drivers/clk/clk-stm32f4.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index 18117ce5ff85..42ca2dd86aea 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = {
>  
>  #define MAX_POST_DIV 3
>  static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
> -       { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
> +       { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
>                  CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
>  
> -       { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
> +       { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
>                  CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
>  
> -       { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
> +       { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
>                  STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
>  };
>  
> -- 
> 2.17.1