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Message-Id: <dbc0ab2e109111ca814e73abb30a1dda5d333dbe.1624449519.git.michal.simek@xilinx.com>
Date: Wed, 23 Jun 2021 13:58:41 +0200
From: Michal Simek <michal.simek@...inx.com>
To: linux-kernel@...r.kernel.org, monstr@...str.eu,
michal.simek@...inx.com, git@...inx.com
Cc: Hyun Kwon <hyun.kwon@...inx.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org
Subject: [PATCH] PCI: xilinx-nwl: Enable the clock through CCF
From: Hyun Kwon <hyun.kwon@...inx.com>
Simply enable clocks. There is no remove function that's why
this should be enough for simple operation.
Signed-off-by: Hyun Kwon <hyun.kwon@...inx.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Signed-off-by: Michal Simek <michal.simek@...inx.com>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 8689311c5ef6..3afd4f89ba77 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -6,6 +6,7 @@
* (C) Copyright 2014 - 2015, Xilinx, Inc.
*/
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@@ -169,6 +170,7 @@ struct nwl_pcie {
u8 last_busno;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
+ struct clk *clk;
raw_spinlock_t leg_mask_lock;
};
@@ -823,6 +825,11 @@ static int nwl_pcie_probe(struct platform_device *pdev)
return err;
}
+ pcie->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(pcie->clk))
+ return PTR_ERR(pcie->clk);
+ clk_prepare_enable(pcie->clk);
+
err = nwl_pcie_bridge_init(pcie);
if (err) {
dev_err(dev, "HW Initialization failed\n");
--
2.32.0
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