linux-kernel - Re: [PATCH] firmware: export x86_64 platform flash bios region via sysfs

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Message-ID: <d61176a0-67cf-268f-8c31-8de8739753c3@immu.ne>
Date:   Wed, 23 Jun 2021 14:17:54 +0200
From:   Hans-Gert Dahmen <hans-gert.dahmen@...u.ne>
To:     David Laight <David.Laight@...LAB.COM>,
        "akpm@...ux-foundation.org" <akpm@...ux-foundation.org>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "philipp.deppenwiese@...u.ne" <philipp.deppenwiese@...u.ne>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>
Subject: Re: [PATCH] firmware: export x86_64 platform flash bios region via
 sysfs

Hi,

these are some good points.

On 23.06.21 00:18, David Laight wrote:
> Are you saying that my 15 year old 64bit Athlon cpu and bios
> have this large SPI flash

No. The reads will wrap, i.e. if your flash is 2MB then it would be 
repeated 8 times in the 16MB window.

> and the required hardware to
> convert bus cycles to serial spi reads?

Yes. The window is part of the DMI interface and the south bridge or PCH 
converts the bus cycles to SPI reads. It is because this region contains 
the reset vector address of your CPU and the very first instruction it 
executes after a reset when the internal setup is done will actually be 
loaded from the serial SPI bus. It is AFAIK part of AMD's original 
64-bit specification.

However, after reading your mail I understand that I should have looked 
up the exact explanations in the respective specs. So to definitively 
answer your question I need to know which south bridge there is in your 
15 year old system and have a look into its datasheet. Do you know which 
one it is by any chance?

Hans-Gert Dahmen