linux-kernel - Re: [PATCH] uio: Fix bus error that access memory mapped by physical

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 23 Jun 2021 20:32:55 +0800
From:   wubian <wubian@...ontech.com>
To:     Greg KH <gregkh@...uxfoundation.org>
Cc:     linux-kernel@...r.kernel.org, catalin.marinas@....com,
        will.deacon@....com
Subject: Re: [PATCH] uio: Fix bus error that access memory mapped by physical



On 2021/6/23 下午5:25, Greg KH wrote:
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing in e-mail?
> 
> A: No.
> Q: Should I include quotations after my reply?
> 
> http://daringfireball.net/2007/07/on_top
> 
> On Wed, Jun 23, 2021 at 04:49:16PM +0800, wubian wrote:
>> First,thanks for your reply
>>
>> I haven’t found this problem on the x86 platform. I only found it on arm64.
>> I used gdb to track memset and found that the bus error in
>> glibc/sysdeps/aarch64/memset.S: dc zva, dst; reference "Architecture
>> Reference ManualArmv8, for Armv8-A architecture profile" manual found that
>> the dc assembly instruction（performance optimization） is related to the
>> operation of the cache, that is to say, there is a bus error in the
>> operation of the cache, and then check the "ARM Cortex-A Series Programmer's
>> Guide for ARMv8-A " manual, found that the armv8 architecture cache has data
>> cache and write buffer, and there are two operation modes write-back and
>> write-through, write operations in these two modes, the data flow will pass
>> through the write buffer, and pgprot_noncached will prohibit data Cache and
>> write buffer, this causes the dc command in memset to fail (bus error), and
>> pgprot_writecombine does not prohibit write buffer, so the dc command in
>> memset is successfully operated when pgprot_writecombine is used.
> 
> Are you sure this is not just a specific hardware platform issue?  Are
> you sure this is going to be correct for _ALL_ arm64 systems?
> 
> Perhaps get the arm64 developers to agree with what is happening here as
> this is the first time anyone has reported this problem.
> 
> What specific platform are you using that this issue happens on?
> 
> thanks,
> 
> greg k-h
> 
> 

I apologize for the kernel mail reply format problem, I will pay 
attention to it in the future.

I only found this problem on Huawei Kunpeng 920 cpu at present, and 
found that some people
have raised similar problems on the Internet.
link：https://github.com/ikwzm/udmabuf/issues/31

@Catalin Marinas @Will Deacon Has anyone reported a similar problem on 
the arm64 platform?