linux-kernel - [PATCH 1/1] config: Enable jh7100 SoC

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Date:   Wed, 23 Jun 2021 21:46:54 +0900
From:   Akira Tsukamoto <akira.tsukamoto@...il.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Atish Patra <atish.patra@....com>,
        Anup Patel <anup.patel@....com>,
        Emil Renner Berthing <kernel@...il.dk>,
        Björn Töpel <bjorn@...nel.org>,
        Sagar Shrikant Kadam <sagar.kadam@...ive.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH 1/1] config: Enable jh7100 SoC


Signed-off-by: Akira Tsukamoto <akira.tsukamoto@...il.com>
---
 arch/riscv/configs/defconfig | 105 +++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 1f2be234b11c..e07d26d2743c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -138,3 +138,108 @@ CONFIG_DEBUG_BLOCK_EXT_DEVT=y
 CONFIG_MEMTEST=y
 # CONFIG_SYSFS_SYSCALL is not set
 CONFIG_EFI=y
+CONFIG_FB_STARFIVE=y
+CONFIG_FB_STARFIVE_HDMI_ADV7513=y
+CONFIG_FB_STARFIVE_HDMI_TDA998X=y
+CONFIG_FB_STARFIVE_SEEED5INCH=y
+CONFIG_FB_STARFIVE_VIDEO=y
+CONFIG_HW_RANDOM_STARFIVE_VIC=y
+CONFIG_SOC_STARFIVE_VIC7100=y
+CONFIG_FPGA_GMAC_FLUSH_DDR=y
+CONFIG_MMC_DW_FLUSH_DDR=y
+CONFIG_USB_CDNS3_HOST_FLUSH_DMA=y
+CONFIG_SOC_STARFIVE_VIC7100_I2C_GPIO=y
+CONFIG_VIDEO_STARFIVE_VIN=y
+CONFIG_VIDEO_STARFIVE_VIN_SENSOR_IMX219=y
+CONFIG_VIDEO_STARFIVE_VIN_SENSOR_OV5640=y
+CONFIG_VIDEO_STARFIVE_VIN_SENSOR_SC2235=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=15
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_EFI_BOOTLOADER_CONTROL=y
+CONFIG_BLK_PM=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_KSM=y
+CONFIG_CMA=y
+CONFIG_CMA_AREAS=7
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PARTITIONED_MASTER=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_DMA=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_STARFIVE_VIC=y
+CONFIG_GPIO_TPS65086=y
+CONFIG_POWER_RESET_TPS65086=y
+CONFIG_MFD_TPS65086=y
+CONFIG_USB_HID=y
+CONFIG_USB_CDNS_SUPPORT=y
+CONFIG_USB_CDNS_HOST=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_SDIO_UART=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_OF=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DW_AXI_DMAC_STARFIVE=y
+CONFIG_COMMON_CLK_SI544=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_SIFIVE_L2=y
+CONFIG_SIFIVE_L2_FLUSH=y
+CONFIG_SIFIVE_L2_FLUSH_START=0x80000000
+CONFIG_SIFIVE_L2_FLUSH_SIZE=0x800000000
+CONFIG_SIFIVE_L2_IRQ_DISABLE=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_SIFIVE_PTC=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_PROC_KCORE=y
+CONFIG_EFIVAR_FS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=640
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_MICREL_PHY=y
-- 
2.17.1