linux-kernel - Re: [PATCH] i2c: cadence: Clear HOLD bit before xfer

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Message-ID: <YNNe63q2T/9ndSgg@kunai>
Date:   Wed, 23 Jun 2021 18:18:51 +0200
From:   Wolfram Sang <wsa@...nel.org>
To:     Raviteja Narayanam <raviteja.narayanam@...inx.com>
Cc:     linux-i2c@...r.kernel.org, michal.simek@...inx.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        git@...inx.com
Subject: Re: [PATCH] i2c: cadence: Clear HOLD bit before xfer_size register
 rolls over

On Tue, Nov 24, 2020 at 01:16:05PM +0530, Raviteja Narayanam wrote:
> On Xilinx zynq SOC if the delay between address register write and
> control register write in cdns_mrecv function is more, the xfer size
> register rolls over and controller is stuck. This is an IP bug and
> is resolved in later versions of IP.
> 
> To avoid this scenario, disable the interrupts on the current processor
> core between the two register writes and enable them later. This can
> help achieve the timing constraint.
> 
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam@...inx.com>

Applied to for-next, thanks!


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