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Message-ID: <800c06ad-1491-c5ba-c650-c78384bf50c9@huawei.com>
Date: Thu, 24 Jun 2021 09:55:53 +0800
From: Zhenyu Ye <yezhenyu2@...wei.com>
To: Will Deacon <will@...nel.org>
CC: Catalin Marinas <catalin.marinas@....com>,
<aneesh.kumar@...ux.ibm.com>, Marc Zyngier <maz@...nel.org>,
<steven.price@....com>, Peter Zijlstra <peterz@...radead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-arch@...r.kernel.org>,
<linux-mm@...ck.org>, Xiexiangyou <xiexiangyou@...wei.com>,
<liushixin2@...wei.com>, huyaqin <huyaqin1@...wei.com>,
<zhurui3@...wei.com>
Subject: Re: [PATCH v1] arm64: tlb: fix the TTL value of tlb_get_level
On 2021/6/23 19:04, Will Deacon wrote:
> On Wed, Jun 23, 2021 at 03:05:22PM +0800, Zhenyu Ye wrote:
>> diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
>> index 61c97d3b58c7..c995d1f4594f 100644
>> --- a/arch/arm64/include/asm/tlb.h
>> +++ b/arch/arm64/include/asm/tlb.h
>> @@ -28,6 +28,10 @@ static void tlb_flush(struct mmu_gather *tlb);
>> */
>> static inline int tlb_get_level(struct mmu_gather *tlb)
>> {
>> + /* The TTL field is only valid for the leaf entry. */
>> + if (tlb->freed_tables)
>> + return 0;
>> +
>> if (tlb->cleared_ptes && !(tlb->cleared_pmds ||
>> tlb->cleared_puds ||
>> tlb->cleared_p4ds))
>
> Thanks. I can't see a better way around this, so I'll queue the patch.
> The stage-2 page-table code looks ok afaict, but please can you check it
> too?
The stage-2 page-table codes seem to be correct to me.
Thanks,
Zhenyu
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