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Message-ID: <f2a2a079-10e8-e8a5-87ea-245e315429f2@gmail.com>
Date: Thu, 24 Jun 2021 14:51:15 +0200
From: Johan Jonker <jbx6244@...il.com>
To: cl@...k-chips.com, heiko@...ech.de
Cc: robh+dt@...nel.org, zhangqing@...k-chips.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
lee.jones@...aro.org
Subject: Re: [PATCH v1 3/3] arm64: dts: rockchip: add pmu and qos nodes for
rk3568
Hi Liang,
The nodes without 'reg' are sort alphabetically.
Nodes with 'reg' are sort on reg number.
pmu: power-management@...90000 {}
sdmmc2: mmc @fe000000 {}
qos_gpu: qos @fe128000 {}
[..]
sdmmc0: mmc @fe2b0000 {}
Johan
On 6/24/21 1:47 PM, cl@...k-chips.com wrote:
> From: Liang Chen <cl@...k-chips.com>
>
> Add the power-management and QoS nodes to the core rk3568 dtsi.
>
> Signed-off-by: Liang Chen <cl@...k-chips.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++
> 1 file changed, 229 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index d225e6a45d5c..2737f26775ff 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3568-power.h>
> #include <dt-bindings/soc/rockchip,boot-mode.h>
> #include <dt-bindings/thermal/thermal.h>
>
> @@ -257,6 +258,234 @@
> status = "disabled";
> };
>
> + pmu: power-management@...90000 {
> + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
> + reg = <0x0 0xfdd90000 0x0 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3568-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* These power domains are grouped by VD_GPU */
> + power-domain@...568_PD_GPU {
> + reg = <RK3568_PD_GPU>;
> + clocks = <&cru ACLK_GPU_PRE>,
> + <&cru PCLK_GPU_PRE>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + /* These power domains are grouped by VD_LOGIC */
> + power-domain@...568_PD_VI {
> + reg = <RK3568_PD_VI>;
> + clocks = <&cru HCLK_VI>,
> + <&cru PCLK_VI>;
> + pm_qos = <&qos_isp>,
> + <&qos_vicap0>,
> + <&qos_vicap1>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_VO {
> + reg = <RK3568_PD_VO>;
> + clocks = <&cru HCLK_VO>,
> + <&cru PCLK_VO>,
> + <&cru ACLK_VOP_PRE>;
> + pm_qos = <&qos_hdcp>,
> + <&qos_vop_m0>,
> + <&qos_vop_m1>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_RGA {
> + reg = <RK3568_PD_RGA>;
> + clocks = <&cru HCLK_RGA_PRE>,
> + <&cru PCLK_RGA_PRE>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_jpeg_dec>,
> + <&qos_jpeg_enc>,
> + <&qos_rga_rd>,
> + <&qos_rga_wr>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_VPU {
> + reg = <RK3568_PD_VPU>;
> + clocks = <&cru HCLK_VPU_PRE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_RKVDEC {
> + clocks = <&cru HCLK_RKVDEC_PRE>;
> + reg = <RK3568_PD_RKVDEC>;
> + pm_qos = <&qos_rkvdec>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_RKVENC {
> + reg = <RK3568_PD_RKVENC>;
> + clocks = <&cru HCLK_RKVENC_PRE>;
> + pm_qos = <&qos_rkvenc_rd_m0>,
> + <&qos_rkvenc_rd_m1>,
> + <&qos_rkvenc_wr_m0>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@...568_PD_PIPE {
> + reg = <RK3568_PD_PIPE>;
> + clocks = <&cru PCLK_PIPE>;
> + pm_qos = <&qos_pcie2x1>,
> + <&qos_pcie3x1>,
> + <&qos_pcie3x2>,
> + <&qos_sata0>,
> + <&qos_sata1>,
> + <&qos_sata2>,
> + <&qos_usb3_0>,
> + <&qos_usb3_1>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_gpu: qos@...28000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe128000 0x0 0x20>;
> + };
> +
> + qos_rkvenc_rd_m0: qos@...38080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138080 0x0 0x20>;
> + };
> +
> + qos_rkvenc_rd_m1: qos@...38100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138100 0x0 0x20>;
> + };
> +
> + qos_rkvenc_wr_m0: qos@...38180 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe138180 0x0 0x20>;
> + };
> +
> + qos_isp: qos@...48000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148000 0x0 0x20>;
> + };
> +
> + qos_vicap0: qos@...48080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148080 0x0 0x20>;
> + };
> +
> + qos_vicap1: qos@...48100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe148100 0x0 0x20>;
> + };
> +
> + qos_vpu: qos@...50000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe150000 0x0 0x20>;
> + };
> +
> + qos_ebc: qos@...58000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158000 0x0 0x20>;
> + };
> +
> + qos_iep: qos@...58100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158100 0x0 0x20>;
> + };
> +
> + qos_jpeg_dec: qos@...58180 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158180 0x0 0x20>;
> + };
> +
> + qos_jpeg_enc: qos@...58200 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158200 0x0 0x20>;
> + };
> +
> + qos_rga_rd: qos@...58280 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158280 0x0 0x20>;
> + };
> +
> + qos_rga_wr: qos@...58300 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe158300 0x0 0x20>;
> + };
> +
> + qos_npu: qos@...80000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe180000 0x0 0x20>;
> + };
> +
> + qos_pcie2x1: qos@...90000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190000 0x0 0x20>;
> + };
> +
> + qos_pcie3x1: qos@...90080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190080 0x0 0x20>;
> + };
> +
> + qos_pcie3x2: qos@...90100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190100 0x0 0x20>;
> + };
> +
> + qos_sata0: qos@...90200 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190200 0x0 0x20>;
> + };
> +
> + qos_sata1: qos@...90280 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190280 0x0 0x20>;
> + };
> +
> + qos_sata2: qos@...90300 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190300 0x0 0x20>;
> + };
> +
> + qos_usb3_0: qos@...90380 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190380 0x0 0x20>;
> + };
> +
> + qos_usb3_1: qos@...90400 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe190400 0x0 0x20>;
> + };
> +
> + qos_rkvdec: qos@...98000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe198000 0x0 0x20>;
> + };
> +
> + qos_hdcp: qos@...a8000 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8000 0x0 0x20>;
> + };
> +
> + qos_vop_m0: qos@...a8080 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8080 0x0 0x20>;
> + };
> +
> + qos_vop_m1: qos@...a8100 {
> + compatible = "rockchip,rk3568-qos", "syscon";
> + reg = <0x0 0xfe1a8100 0x0 0x20>;
> + };
> +
> sdmmc2: mmc@...00000 {
> compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xfe000000 0x0 0x4000>;
>
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