lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20210625164834.GY22278@shell.armlinux.org.uk>
Date:   Fri, 25 Jun 2021 17:48:34 +0100
From:   "Russell King (Oracle)" <linux@...linux.org.uk>
To:     "Voon, Weifeng" <weifeng.voon@...el.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        "Ling, Pei Lee" <pei.lee.ling@...el.com>,
        Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Jose Abreu <joabreu@...opsys.com>,
        "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        "Ong, Boon Leong" <boon.leong.ong@...el.com>,
        Wong Vee Khee <vee.khee.wong@...ux.intel.com>,
        "Wong, Vee Khee" <vee.khee.wong@...el.com>,
        "Tan, Tee Min" <tee.min.tan@...el.com>,
        "Sit, Michael Wei Hong" <michael.wei.hong.sit@...el.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-stm32@...md-mailman.stormreply.com" 
        <linux-stm32@...md-mailman.stormreply.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL
 settings in stmmac_resume()

On Fri, Jun 25, 2021 at 03:58:17PM +0000, Voon, Weifeng wrote:
> > > No, the interrupt will not be discarded. If the PHY is in interrupt
> > > mode, the interrupt handler will triggers and ISR will clear the WOL
> > status bit.
> > > The condition here is when the PHY is in polling mode, the PHY driver
> > > does not have any other mechanism to clear the WOL interrupt status bit.
> > > Hence, we need to go through the PHY set_wol() again.
> > 
> > I would say you have a broken setup. If you are explicitly using the
> > interrupt as a wakeup source, you need to be servicing the interrupt. You
> > cannot use polled mode.
>  
> Sorry for the confusion. But I would like to clarify the I should use the
> term of "WOL event status" rather than "WOL interrupt status". 
> For interrupt mode, clearing the "WOL interrupt status" register will auto
> clear the "WOL event status".
> For polling mode, the phy driver can manually clear the "WOL event status" by
> setting 1 to "Clear WOL Status" bit.  

If WOL raises an interrupt signal from the PHY, but the PHY interrupt
signal is not wired, how does the wakeup happen? What is the PHY
interrupt wired to?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ