linux-kernel - Re: [PATCH v2 2/2] MIPS: Malta: Do not byte-swap accesses to the CBUS UART

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Message-ID: <CAAdtpL6m6zRG7ruYdsjPjbuzuT64ZiBK9tuwcUGEcgkgTfFEmA@mail.gmail.com>
Date:   Sat, 26 Jun 2021 18:44:27 +0200
From:   Philippe Mathieu-Daudé <f4bug@...at.org>
To:     "Maciej W. Rozycki" <macro@...am.me.uk>
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jiri Slaby <jirislaby@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        "open list:BROADCOM NVRAM DRIVER" <linux-mips@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        stable@...r.kernel.org
Subject: Re: [PATCH v2 2/2] MIPS: Malta: Do not byte-swap accesses to the CBUS UART

On Sat, Jun 26, 2021 at 6:11 AM Maciej W. Rozycki <macro@...am.me.uk> wrote:
>
> Correct big-endian accesses to the CBUS UART, a Malta on-board discrete
> TI16C550C part wired directly to the system controller's device bus, and
> do not use byte swapping with the 32-bit accesses to the device.
>
> The CBUS is used for devices such as the boot flash memory needed early
> on in system bootstrap even before PCI has been initialised.  Therefore
> it uses the system controller's device bus, which follows the endianness
> set with the CPU, which means no byte-swapping is ever required for data
> accesses to CBUS, unlike with PCI.
>
> The CBUS UART uses the UPIO_MEM32 access method, that is the `readl' and
> `writel' MMIO accessors, which on the MIPS platform imply byte-swapping
> with PCI systems.  Consequently the wrong byte lane is accessed with the
> big-endian configuration and the UART is not correctly accessed.
>
> As it happens the UPIO_MEM32BE access method makes use of the `ioread32'
> and `iowrite32' MMIO accessors, which still use `readl' and `writel'
> respectively, however they byte-swap data passed, effectively cancelling
> swapping done with the accessors themselves and making it suitable for
> the CBUS UART.
>
> Make the CBUS UART switch between UPIO_MEM32 and UPIO_MEM32BE then,
> based on the endianness selected.  With this change in place the device
> is correctly recognised with big-endian Malta at boot, along with the
> Super I/O devices behind PCI:
>
> Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
> printk: console [ttyS0] disabled
> serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
> printk: console [ttyS0] enabled
> printk: bootconsole [uart8250] disabled
> serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
> serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20, base_baud = 230400) is a 16550A
>
> Signed-off-by: Maciej W. Rozycki <macro@...am.me.uk>
> Fixes: e7c4782f92fc ("[MIPS] Put an end to <asm/serial.h>'s long and annyoing existence")
> Cc: stable@...r.kernel.org # v2.6.23+
> ---
> Changes from v1:
>
> - Remove console message duplicates from the commit description.
> ---
>  arch/mips/mti-malta/malta-platform.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@...at.org>