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Message-Id: <20210627114616.717101-2-bhupesh.sharma@linaro.org>
Date: Sun, 27 Jun 2021 17:16:14 +0530
From: Bhupesh Sharma <bhupesh.sharma@...aro.org>
To: linux-arm-msm@...r.kernel.org
Cc: bhupesh.sharma@...aro.org, bhupesh.linux@...il.com,
balbi@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, robh+dt@...nel.org, agross@...nel.org,
Bjorn Andersson <bjorn.andersson@...aro.org>
Subject: [PATCH v2 1/3] arm64: dts: qcom: Use correct naming for dwc3 usb nodes in dts files
The dwc3 usb nodes in several arm64 qcom dts are currently named
differently, somewhere as 'usb@<addr>' and somewhere as 'dwc3@<addr>',
leading to some confusion when one sees the entries in sysfs or
dmesg:
[ 1.943482] dwc3 a600000.usb: Adding to iommu group 1
[ 2.266127] dwc3 a800000.dwc3: Adding to iommu group 2
Name the usb nodes as 'usb@<addr>' for consistency, which is
the correct convention as per the 'snps,dwc3' dt-binding as
well (see [1]).
[1]. Documentation/devicetree/bindings/usb/snps,dwc3.yaml
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
---
arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index f9f0b5aa6a26..662f2f246b9b 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -430,7 +430,7 @@ usb3: usb@...f8800 {
power-domains = <&gcc USB30_GDSC>;
qcom,select-utmi-as-pipe-clk;
- dwc3@...00000 {
+ usb@...00000 {
compatible = "snps,dwc3";
reg = <0xf9200000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 612dda0fef43..9c931beeb614 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2389,7 +2389,7 @@ usb_2: usb@...8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
- usb_2_dwc3: dwc3@...0000 {
+ usb_2_dwc3: usb@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4798368b02ef..9c1462cc9dad 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2321,7 +2321,7 @@ usb_1: usb@...8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
- usb_1_dwc3: dwc3@...0000 {
+ usb_1_dwc3: usb@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -2372,7 +2372,7 @@ usb_2: usb@...8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
- usb_2_dwc3: dwc3@...0000 {
+ usb_2_dwc3: usb@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0d16392bb976..a631d58166b1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1273,7 +1273,7 @@ usb_1: usb@...8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
- usb_1_dwc3: dwc3@...0000 {
+ usb_1_dwc3: usb@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -1317,7 +1317,7 @@ usb_2: usb@...8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
- usb_2_dwc3: dwc3@...0000 {
+ usb_2_dwc3: usb@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
--
2.31.1
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