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Message-Id: <1624904444-2618-2-git-send-email-zhouyanjie@wanyeetech.com>
Date: Tue, 29 Jun 2021 02:20:34 +0800
From: 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com>
To: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org
Cc: linux-mips@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
paul@...pouillou.net, dongsheng.qiu@...enic.com,
aric.pzqi@...enic.com, rick.tyliu@...enic.com,
sihui.liu@...enic.com, jun.jiang@...enic.com,
sernia.zhou@...mail.com
Subject: [PATCH v5 01/11] clk: JZ4780: Add function for disable the second core.
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
Reviewed-by: Paul Cercueil <paul@...pouillou.net>
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
v3->v4:
No change.
v4->v5:
No change.
drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 0268d23..dcca74e 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw)
return 0;
}
+static void jz4780_core1_disable(struct clk_hw *hw)
+{
+ struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+ struct ingenic_cgu *cgu = ingenic_clk->cgu;
+ unsigned long flags;
+ u32 lcr, clkgr1;
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ lcr = readl(cgu->base + CGU_REG_LCR);
+ lcr |= LCR_PD_SCPU;
+ writel(lcr, cgu->base + CGU_REG_LCR);
+
+ clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
+ clkgr1 |= CLKGR1_CORE1;
+ writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+}
+
static const struct clk_ops jz4780_core1_ops = {
.enable = jz4780_core1_enable,
+ .disable = jz4780_core1_disable,
};
static const s8 pll_od_encoding[16] = {
--
2.7.4
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