linux-kernel - Re: [PATCH] thermal: int340x: processor

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 28 Jun 2021 22:42:04 +0200
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
        rui.zhang@...el.com, amitk@...nel.org
Cc:     linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] thermal: int340x: processor_thermal: Fix tcc setting

On 28/06/2021 22:10, Srinivas Pandruvada wrote:
> The following fixes are done for tcc sysfs interface:
> - TCC is 6 bits only from bit 29-24
> - TCC of 0 is valid
> - When BIT(31) is set, this register is read only
> - Check for invalid tcc value
> - Error for negative values
> 

Fixes: fdf4f2fb8e899 ("Export sysfs interface for TCC")

?

> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
> ---
>  .../processor_thermal_device.c                | 20 +++++++++++--------
>  1 file changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c
> index de4fc640deb0..0f0038af2ad4 100644
> --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c
> +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c
> @@ -78,24 +78,27 @@ static ssize_t tcc_offset_degree_celsius_show(struct device *dev,
>  	if (err)
>  		return err;
>  
> -	val = (val >> 24) & 0xff;
> +	val = (val >> 24) & 0x3f;
>  	return sprintf(buf, "%d\n", (int)val);
>  }
>  
> -static int tcc_offset_update(int tcc)
> +static int tcc_offset_update(unsigned int tcc)
>  {
>  	u64 val;
>  	int err;
>  
> -	if (!tcc)
> +	if (tcc > 63)
>  		return -EINVAL;
>  
>  	err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
>  	if (err)
>  		return err;
>  
> -	val &= ~GENMASK_ULL(31, 24);
> -	val |= (tcc & 0xff) << 24;
> +	if (val & BIT(31))
> +		return -EPERM;
> +
> +	val &= ~GENMASK_ULL(29, 24);
> +	val |= (tcc & 0x3f) << 24;
>  
>  	err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val);
>  	if (err)
> @@ -104,14 +107,15 @@ static int tcc_offset_update(int tcc)
>  	return 0;
>  }
>  
> -static int tcc_offset_save;
> +static unsigned int tcc_offset_save;
>  
>  static ssize_t tcc_offset_degree_celsius_store(struct device *dev,
>  				struct device_attribute *attr, const char *buf,
>  				size_t count)
>  {
> +	unsigned int tcc;
>  	u64 val;
> -	int tcc, err;
> +	int err;
>  
>  	err = rdmsrl_safe(MSR_PLATFORM_INFO, &val);
>  	if (err)
> @@ -120,7 +124,7 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev,
>  	if (!(val & BIT(30)))
>  		return -EACCES;
>  
> -	if (kstrtoint(buf, 0, &tcc))
> +	if (kstrtouint(buf, 0, &tcc))
>  		return -EINVAL;
>  
>  	err = tcc_offset_update(tcc);
> 


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog