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Message-ID: <BYAPR02MB394184FD49527801FE8E5389B7039@BYAPR02MB3941.namprd02.prod.outlook.com>
Date:   Mon, 28 Jun 2021 06:59:41 +0000
From:   Rajan Vaja <RAJANV@...inx.com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "kristo@...nel.org" <kristo@...nel.org>,
        "lee.jones@...aro.org" <lee.jones@...aro.org>,
        Michal Simek <michals@...inx.com>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "quanyang.wang@...driver.com" <quanyang.wang@...driver.com>
CC:     "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock
 flags

Hi Stephen,

> -----Original Message-----
> From: Stephen Boyd <sboyd@...nel.org>
> Sent: Friday, June 25, 2021 4:22 PM
> To: Rajan Vaja <RAJANV@...inx.com>; kristo@...nel.org; lee.jones@...aro.org;
> Michal Simek <michals@...inx.com>; mturquette@...libre.com;
> quanyang.wang@...driver.com
> Cc: linux-clk@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; Rajan Vaja <RAJANV@...inx.com>
> Subject: Re: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock
> flags
> 
> Quoting Rajan Vaja (2021-06-24 05:16:30)
> > diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> > index db8d0d7161ce..af06a195ec46 100644
> > --- a/drivers/clk/zynqmp/clkc.c
> > +++ b/drivers/clk/zynqmp/clkc.c
> > @@ -271,6 +271,34 @@ static int zynqmp_pm_clock_get_topology(u32
> clock_id, u32 index,
> >         return ret;
> >  }
> >
> > +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
> > +{
> > +       unsigned long ccf_flag = 0;
> > +
> > +       if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
> > +               ccf_flag |= CLK_SET_RATE_GATE;
> > +       if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
> > +               ccf_flag |= CLK_SET_PARENT_GATE;
> > +       if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
> > +               ccf_flag |= CLK_SET_RATE_PARENT;
> > +       if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
> > +               ccf_flag |= CLK_IGNORE_UNUSED;
> > +       if (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE)
> > +               ccf_flag |= CLK_GET_RATE_NOCACHE;
> 
> Does the firmware really use all these flags? Ideally we get rid of the
> above two.
> 
> > +       if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
> > +               ccf_flag |= CLK_SET_RATE_NO_REPARENT;
> > +       if (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE)
> > +               ccf_flag |= CLK_GET_ACCURACY_NOCACHE;
> > +       if (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES)
> > +               ccf_flag |= CLK_RECALC_NEW_RATES;
> 
> And this one.
> 
> > +       if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE)
> > +               ccf_flag |= CLK_SET_RATE_UNGATE;
> > +       if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
> > +               ccf_flag |= CLK_IS_CRITICAL;
> 
> And this one.
> 
> I worry that supporting all these flags will mean we can never get rid
> of them. And we currently don't support setting critical via DT, which
> is essentially another firmware interface like this one.
[Rajan] firmware is using below flags:
ZYNQMP_CLK_SET_RATE_GATE
ZYNQMP_CLK_SET_PARENT_GATE
ZYNQMP_CLK_SET_RATE_PARENT
ZYNQMP_CLK_IGNORE_UNUSED
ZYNQMP_CLK_SET_RATE_NO_REPARENT
ZYNQMP_CLK_IS_CRITICAL

Other flags are unused. I will remove unused flags in next version.

Thanks,
Rajan
> 
> > +
> > +       return ccf_flag;
> > +}
> > +
> >  /**
> >   * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
> >   *                                     clock framework

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