linux-kernel - Re: Candidate Linux ABI for Intel AMX and hypothetical new related features

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Message-ID: <87tulirw5y.fsf@oldenburg.str.redhat.com>
Date:   Mon, 28 Jun 2021 14:49:45 +0200
From:   Florian Weimer <fweimer@...hat.com>
To:     "Enrico Weigelt, metux IT consult" <lkml@...ux.net>
Cc:     Len Brown <lenb@...nel.org>, Peter Zijlstra <peterz@...radead.org>,
        Dave Hansen via Libc-alpha <libc-alpha@...rceware.org>,
        Dave Hansen <dave.hansen@...el.com>,
        Rich Felker <dalias@...c.org>,
        Linux API <linux-api@...r.kernel.org>,
        "Bae, Chang Seok" <chang.seok.bae@...el.com>,
        X86 ML <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>,
        Kyle Huey <me@...ehuey.com>, Borislav Petkov <bp@...en8.de>,
        Andy Lutomirski <luto@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Keno Fischer <keno@...iacomputing.com>,
        Arjan van de Ven <arjan@...ux.intel.com>,
        Willy Tarreau <w@....eu>
Subject: Re: Candidate Linux ABI for Intel AMX and hypothetical new related
 features

* Enrico Weigelt:

> On 24.06.21 01:11, Len Brown wrote:
>>>    x86 CPU features detection for applications (and AMX)
>>>    <https://lore.kernel.org/linux-api/87tulo39ms.fsf@oldenburg.str.redhat.com/>
>> FWIW, I didn't receive it, because you excluded
>> linux-kernel@...r.kernel.org
>
> me neither :(
>
> Maybe just repost it to LKML ?

Isn't it sufficient to start Cc:ing the list?

> You mention the interface *was* designed with cpu features remaining
> constant over a process' lifetime. Between the line I'm reading that
> this might not be the case anymore.
>
> How could that happen ? Process migration on a different CPU (or perhaps
> on a different host) ?

AMX will be shown as enabled in the hardware, but trap into the kernel
on first use.  The kernel developers prefer a model where it is checked
that the process has previously enabled the feature explicitly, instead
relying on lazy initialization as part of the trap (as intended by the
hardware design).  This means that the usual CPUID/XCR0 approach (which
is reflected in the glibc feature) will not work.

Now it turns out that we can still support this in glibc because of the
pointer indirection, but only if the kernel provides a bit we can read
in thread-specific data.

> Damn, how could the cpu designers come up with such weird concepts
> in the first place ? :o

It's not the CPU designers. The CPU behaves according to the old model.
(I consider the old model a success, despite all the challenges, but not
everyone agrees, obviosly.)

Thanks,
Florian