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Date: Sun, 27 Jun 2021 19:49:37 -0700 From: Stephen Boyd <sboyd@...nel.org> To: Michael Turquette <mturquette@...libre.com>, Paul Cercueil <paul@...pouillou.net> Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org, list@...ndingux.net, 周琰杰 <zhouyanjie@...yeetech.com>, Paul Cercueil <paul@...pouillou.net> Subject: Re: [PATCH v2 2/6] clk: Support bypassing dividers Quoting Paul Cercueil (2021-05-30 09:49:19) > When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU > code expects the mux to be applied first, the divider second. > > On the JZ4760, and maybe on some other SoCs, some clocks also have a mux > setting and a divider, but the divider is not applied to all parents > selectable from the mux. > > This could be solved by creating two clocks, one with CGU_CLK_DIV and > one with CGU_CLK_MUX, but that would increase the number of clocks. > > Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit > corresponding to the parent clock's index is set, the divider is > bypassed. > > Signed-off-by: Paul Cercueil <paul@...pouillou.net> > --- Applied to clk-next
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