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Message-Id: <FZKIVQ.1Y3JQ8K8BRMB3@crapouillou.net>
Date: Wed, 30 Jun 2021 13:21:15 +0100
From: Paul Cercueil <paul@...pouillou.net>
To: 周琰杰 <zhouyanjie@...yeetech.com>
Cc: tsbogend@...ha.franken.de, mturquette@...libre.com,
sboyd@...nel.org, robh+dt@...nel.org, linux-mips@...r.kernel.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, dongsheng.qiu@...enic.com,
aric.pzqi@...enic.com, rick.tyliu@...enic.com,
sihui.liu@...enic.com, jun.jiang@...enic.com,
sernia.zhou@...mail.com
Subject: Re: [PATCH v4 4/5] MIPS: CI20: Reduce clocksource to 750 kHz.
Hi Zhou,
Le sam., juin 26 2021 at 14:18:40 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com> a écrit :
> The original clock (3 MHz) is too fast for the clocksource,
> there will be a chance that the system may get stuck.
>
> Reported-by: Nikolaus Schaller <hns@...delico.com>
> Tested-by: Nikolaus Schaller <hns@...delico.com> # on CI20
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
Acked-by: Paul Cercueil <paul@...pouillou.net>
Cheers,
-Paul
> ---
>
> Notes:
> v4:
> New patch.
>
> arch/mips/boot/dts/ingenic/ci20.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 8877c62..3a4eaf1 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -525,10 +525,10 @@
>
> &tcu {
> /*
> - * 750 kHz for the system timer and 3 MHz for the clocksource,
> + * 750 kHz for the system timer and clocksource,
> * use channel #0 for the system timer, #1 for the clocksource.
> */
> assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> <&tcu TCU_CLK_OST>;
> - assigned-clock-rates = <750000>, <3000000>, <3000000>;
> + assigned-clock-rates = <750000>, <750000>, <3000000>;
> };
> --
> 2.7.4
>
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