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Message-Id: <20210630152828.162659-3-nchatrad@amd.com>
Date: Wed, 30 Jun 2021 20:58:23 +0530
From: Naveen Krishna Chatradhi <nchatrad@....com>
To: linux-edac@...r.kernel.org, x86@...nel.org
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, mingo@...hat.com,
mchehab@...nel.org
Subject: [PATCH 2/7] x86/amd_nb: Add support for northbridges on Aldebaran
From: Muralidhara M K <muralimk@....com>
On newer heterogeneous systems from AMD, there is a possibility of
having GPU nodes along with CPU nodes with the MCA banks. The GPU
nodes (noncpu nodes) starts enumerating from northbridge index 8.
Aldebaran GPUs have 2 root ports, with 4 misc port for each root.
Signed-off-by: Muralidhara M K <muralimk@....com>
Signed-off-by: Naveen Krishna Chatradhi <nchatrad@....com>
---
arch/x86/include/asm/amd_nb.h | 6 ++++
arch/x86/kernel/amd_nb.c | 62 ++++++++++++++++++++++++++++++++---
2 files changed, 63 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 00d1a400b7a1..e71581cf00e3 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -79,6 +79,12 @@ struct amd_northbridge_info {
#ifdef CONFIG_AMD_NB
+/*
+ * On Newer heterogeneous systems from AMD with CPU and GPU nodes connected
+ * via xGMI links, the NON CPU Nodes are enumerated from index 8
+ */
+#define NONCPU_NODE_INDEX 8
+
u16 amd_nb_num(void);
bool amd_nb_has_feature(unsigned int feature);
struct amd_northbridge *node_to_amd_nb(int node);
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 5884dfa619ff..489003e850dd 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -26,6 +26,8 @@
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
+#define PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT 0x14bb
+#define PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4 0x14d4
/* Protect the PCI config register pairs used for SMN. */
static DEFINE_MUTEX(smn_mutex);
@@ -94,6 +96,21 @@ static const struct pci_device_id hygon_nb_link_ids[] = {
{}
};
+static const struct pci_device_id amd_noncpu_root_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_ROOT) },
+ {}
+};
+
+static const struct pci_device_id amd_noncpu_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F3) },
+ {}
+};
+
+static const struct pci_device_id amd_noncpu_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ALDEBARAN_DF_F4) },
+ {}
+};
+
const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
{ 0x00, 0x18, 0x20 },
{ 0xff, 0x00, 0x20 },
@@ -182,11 +199,16 @@ int amd_cache_northbridges(void)
const struct pci_device_id *misc_ids = amd_nb_misc_ids;
const struct pci_device_id *link_ids = amd_nb_link_ids;
const struct pci_device_id *root_ids = amd_root_ids;
+
+ const struct pci_device_id *noncpu_misc_ids = amd_noncpu_nb_misc_ids;
+ const struct pci_device_id *noncpu_link_ids = amd_noncpu_nb_link_ids;
+ const struct pci_device_id *noncpu_root_ids = amd_noncpu_root_ids;
+
struct pci_dev *root, *misc, *link;
struct amd_northbridge *nb;
u16 roots_per_misc = 0;
- u16 misc_count = 0;
- u16 root_count = 0;
+ u16 misc_count = 0, misc_count_noncpu = 0;
+ u16 root_count = 0, root_count_noncpu = 0;
u16 i, j;
if (amd_northbridges.num)
@@ -205,10 +227,16 @@ int amd_cache_northbridges(void)
if (!misc_count)
return -ENODEV;
+ while ((misc = next_northbridge(misc, noncpu_misc_ids)) != NULL)
+ misc_count_noncpu++;
+
root = NULL;
while ((root = next_northbridge(root, root_ids)) != NULL)
root_count++;
+ while ((root = next_northbridge(root, noncpu_root_ids)) != NULL)
+ root_count_noncpu++;
+
if (root_count) {
roots_per_misc = root_count / misc_count;
@@ -222,15 +250,27 @@ int amd_cache_northbridges(void)
}
}
- nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
+ /*
+ * The valid amd_northbridges are in between (0 ~ misc_count) and
+ * (NONCPU_NODE_INDEX ~ NONCPU_NODE_INDEX + misc_count_noncpu)
+ */
+ if (misc_count_noncpu)
+ /*
+ * There are NONCPU Nodes with pci root ports starting at index 8
+ * allocate few extra cells for simplicity in handling the indexes
+ */
+ amd_northbridges.num = NONCPU_NODE_INDEX + misc_count_noncpu;
+ else
+ amd_northbridges.num = misc_count;
+
+ nb = kcalloc(amd_northbridges.num, sizeof(struct amd_northbridge), GFP_KERNEL);
if (!nb)
return -ENOMEM;
amd_northbridges.nb = nb;
- amd_northbridges.num = misc_count;
link = misc = root = NULL;
- for (i = 0; i < amd_northbridges.num; i++) {
+ for (i = 0; i < misc_count; i++) {
node_to_amd_nb(i)->root = root =
next_northbridge(root, root_ids);
node_to_amd_nb(i)->misc = misc =
@@ -251,6 +291,18 @@ int amd_cache_northbridges(void)
root = next_northbridge(root, root_ids);
}
+ link = misc = root = NULL;
+ if (misc_count_noncpu) {
+ for (i = NONCPU_NODE_INDEX; i < NONCPU_NODE_INDEX + misc_count_noncpu; i++) {
+ node_to_amd_nb(i)->root = root =
+ next_northbridge(root, noncpu_root_ids);
+ node_to_amd_nb(i)->misc = misc =
+ next_northbridge(misc, noncpu_misc_ids);
+ node_to_amd_nb(i)->link = link =
+ next_northbridge(link, noncpu_link_ids);
+ }
+ }
+
if (amd_gart_present())
amd_northbridges.flags |= AMD_NB_GART;
--
2.25.1
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