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Message-Id: <1625087320-194204-6-git-send-email-kan.liang@linux.intel.com>
Date: Wed, 30 Jun 2021 14:08:29 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org, mingo@...hat.com, gregkh@...uxfoundation.org,
acme@...nel.org, linux-kernel@...r.kernel.org
Cc: eranian@...gle.com, namhyung@...nel.org, jolsa@...hat.com,
ak@...ux.intel.com, yao.jin@...ux.intel.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH V4 05/16] perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support
From: Kan Liang <kan.liang@...ux.intel.com>
M2PCIe* blocks manage the interface between the mesh and each IIO stack.
The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.
Reviewed-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/intel/uncore_snbep.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 8cefeeb..b1bc82c 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5470,13 +5470,18 @@ static struct intel_uncore_type spr_uncore_irp = {
};
+static struct intel_uncore_type spr_uncore_m2pcie = {
+ SPR_UNCORE_COMMON_FORMAT(),
+ .name = "m2pcie",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_chabox,
&spr_uncore_iio,
&spr_uncore_irp,
- NULL,
+ &spr_uncore_m2pcie,
NULL,
NULL,
NULL,
--
2.7.4
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