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Message-ID: <CAL_JsqLHp3kBc1VtGVRxVr_k69GqSC_JX88jo3stdM4W9Qq6AQ@mail.gmail.com>
Date: Thu, 1 Jul 2021 09:25:01 -0600
From: Rob Herring <robh@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
devicetree@...r.kernel.org, PCI <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
hemantk@...eaurora.org,
Siddartha Mohanadoss <smohanad@...eaurora.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Sriharsha Allenki <sallenki@...eaurora.org>,
skananth@...eaurora.org, vpernami@...eaurora.org,
Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
Subject: Re: [PATCH v5 0/3] Add Qualcomm PCIe Endpoint driver support
On Tue, Jun 29, 2021 at 9:47 PM Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org> wrote:
>
> Hello,
>
> This series adds support for Qualcomm PCIe Endpoint controller found
> in platforms like SDX55. The Endpoint controller is based on the designware
> core with additional Qualcomm wrappers around the core.
>
> The driver is added separately unlike other Designware based drivers that
> combine RC and EP in a single driver. This is done to avoid complexity and
> to maintain this driver autonomously.
>
> The driver has been validated with an out of tree MHI function driver on
> SDX55 based Telit FN980 EVB connected to x86 host machine over PCIe.
>
> Thanks,
> Mani
>
> Changes in v5:
>
> * Removed the DBI register settings that are not needed
> * Used the standard definitions available in pci_regs.h
> * Added defines for all the register fields
> * Removed the left over code from previous iteration
>
> Changes in v4:
>
> * Removed the active_config settings needed for IPA integration
> * Switched to writel for couple of relaxed versions that sneaked in
I thought we resolved this discussion. Use _relaxed variants unless
you need the stronger ones.
Rob
>
> Changes in v3:
>
> * Lot of minor cleanups to the driver patch based on review from Bjorn and Stan.
> * Noticeable changes are:
> - Got rid of _relaxed calls and used readl/writel
> - Got rid of separate TCSR memory region and used syscon for getting the
> register offsets for Perst registers
> - Changed the wake gpio handling logic
> - Added remove() callback and removed "suppress_bind_attrs"
> - stop_link() callback now just disables PERST IRQ
> * Added MMIO region and doorbell interrupt to the binding
> * Added logic to write MMIO physicall address to MHI base address as it is
> for the function driver to work
>
> Changes in v2:
>
> * Addressed the comments from Rob on bindings patch
> * Modified the driver as per binding change
> * Fixed the warnings reported by Kbuild bot
> * Removed the PERST# "enable_irq" call from probe()
>
> Manivannan Sadhasivam (3):
> dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP
> controller
> PCI: dwc: Add Qualcomm PCIe Endpoint controller driver
> MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding
>
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++
> MAINTAINERS | 10 +-
> drivers/pci/controller/dwc/Kconfig | 10 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 742 ++++++++++++++++++
> 5 files changed, 922 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> create mode 100644 drivers/pci/controller/dwc/pcie-qcom-ep.c
>
> --
> 2.25.1
>
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