linux-kernel - Re: [PATCH v3 4/4] PCIe: qcom: Add support to control pipe clk mux

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Message-ID: <c334a6d11fae5bd135a94ab5c66b3f97@codeaurora.org>
Date:   Mon, 05 Jul 2021 11:48:37 +0530
From:   Prasad Malisetty <pmaliset@...eaurora.org>
To:     agross@...nel.org, bjorn.andersson@...aro.org, bhelgaas@...gle.com,
        robh+dt@...nel.org, swboyd@...omium.org, lorenzo.pieralisi@....com,
        svarbanov@...sol.com
Cc:     devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
        mgautam@...eaurora.org, dianders@...omium.org, mka@...omium.org,
        sanm@...eaurora.org
Subject: Re: [PATCH v3 4/4] PCIe: qcom: Add support to control pipe clk mux

On 2021-06-22 21:30, Prasad Malisetty wrote:
> pipe-clk mux needs to switch between pipe_clk
> and XO as part of LPM squence. This is done by setting
> pipe_clk mux as parent of pipe_clk after phy init.
> This is a new requirement for sc7280.
> For accessing to DBI registers during L23,
> need to switch the pipe clock with free-running
> clock (TCXO) using GCC’s registers
> 
> Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8a7a300..80e9ee4 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {
>  	struct regulator_bulk_data supplies[2];
>  	struct reset_control *pci_reset;
>  	struct clk *pipe_clk;
> +	struct clk *pipe_clk_mux;
> +	struct clk *pipe_ext_src;
> +	struct clk *ref_clk_src;
>  };
> 
>  union qcom_pcie_resources {
> @@ -1167,6 +1170,20 @@ static int qcom_pcie_get_resources_2_7_0(struct
> qcom_pcie *pcie)
>  	if (ret < 0)
>  		return ret;
> 
> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) {
> +		res->pipe_clk_mux = devm_clk_get(dev, "pipe_mux");
> +		if (IS_ERR(res->pipe_clk_mux))
> +			return PTR_ERR(res->pipe_clk_mux);
> +
> +		res->pipe_ext_src = devm_clk_get(dev, "phy_pipe");
> +		if (IS_ERR(res->pipe_ext_src))
> +			return PTR_ERR(res->pipe_ext_src);
> +
> +		res->ref_clk_src = devm_clk_get(dev, "ref");
> +		if (IS_ERR(res->ref_clk_src))
> +			return PTR_ERR(res->ref_clk_src);
> +	}
> +
>  	res->pipe_clk = devm_clk_get(dev, "pipe");
>  	return PTR_ERR_OR_ZERO(res->pipe_clk);
>  }
> @@ -1255,6 +1272,11 @@ static void qcom_pcie_deinit_2_7_0(struct
> qcom_pcie *pcie)
>  static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
>  {
>  	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280"))
> +		clk_set_parent(res->pipe_clk_mux, res->pipe_ext_src);
> 
>  	return clk_prepare_enable(res->pipe_clk);
>  }


Hi All,

Greetings of the day !!

Could you please provide your comments on updated change series

Thanks
-Prasad