Message-ID: <CAJU4x8t+aOqq82EJMUNDpWiE3GPeyZkjFhy=AkmctcDE3mx6fA@mail.gmail.com>
Date:   Tue, 6 Jul 2021 18:56:57 +0800
From:   Renius Chen <reniuschengl@...il.com>
To:     Ulf Hansson <ulf.hansson@...aro.org>
Cc:     Adrian Hunter <adrian.hunter@...el.com>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Ben Chuang <Ben.Chuang@...esyslogic.com.tw>
Subject: Re: [PATCH] [v2] mmc: sdhci-pci-gli: Improve Random 4K Read
 Performance of GL9763E

Ulf Hansson <ulf.hansson@...aro.org> 於 2021年7月6日 週二 下午6:08寫道：
>
> [...]
>
> > > > Thanks for your explanation.
> > > >
> > > > I think there may be some misunderstandings here.
> > >
> > > I fully understand what you want to do.
> > >
> > > >
> > > > Our purpose is to avoid our GL9763e from entering ASPM L1 state during
> > > > a sequence of 4K read requests. So we don't have to consider about the
> > > > behavior/performance of the eMMC/SD card and what eMMC/SD card that is
> > > > being used. We just need to know what kind of requests we are
> > > > receiving now from the PCIe root port.
> > > >
> > > > Besides, the APSM L1 is purely hardware behavior in GL9763e and has no
> > > > corresponding relationship with runtime PM. It's not activated by
> > > > driver and the behaviors are not handled by software. I think runtime
> > > > PM is used to handle the behaviors of D0/D3 of the device, but not the
> > > > link status of ASPM L0s, L1, etc.
> > >
> > > Maybe runtime PM isn't the perfect fit for this type of use case.
> > >
> > > That still doesn't matter to to me, I will not accept this kind of
> > > governor/policy based code for use cases, in drivers. It doesn't
> > > belong there.
> > >
> >
> > Hi Ulf,
> >
> > The behavior of this patch is to set the value of a GL9763e vendor
> > specified register. Why it doesn't belong to GL9763e driver but other
> > common codes?
>
> Let me try one more time.
>
> The code that is needed to put the GL9763e HW into low power state
> (writing to GL9763e specific register) certainly belongs in the
> driver.
>
> The code that monitors for a specific use case does not.
>
> >
> > > >
> > > > I agree that the policy of balancing performance vs the energy cost is
> > > > a generic problem that all mmc drivers share. But our driver of
> > > > GL9763e is a host driver, the setting in this patch is also only for
> > > > GL9763e, could not be used by other devices. It depends on our
> > > > specific hardware design so that it is not a generic solution or
> > > > policy. So I think to implement such a patch in our specific GL9763e
> > > > driver to execute the specific actions just for our hardware design is
> > > > reasonable.
> > >
> > > From the use case point of view, the GL9763e hardware design isn't at
> > > all specific.
> > >
> > > In many cases, controllers/platforms have support for low power states
> > > that one want to enter to avoid wasting energy. The difficult part is
> > > to know *when* it makes sense to enter a low power state, as it also
> > > introduces a latency when the power needs to be restored for the
> > > device, to allow it to serve a new request.
> > >
> > > To me, it sounds like you may have been too aggressive on avoid
> > > wasting energy. If I understand correctly the idle period you use is
> > > 20/21 us, while most other drivers use 50-100 ms as idle period.
> > >
> >
> > Yes, according to our customer's test for the GL9763e, if the ASPM L1
> > entry delay of GL9763e, which is the idle period you mentioned, is
> > larger than 20/21 us, it will not pass the PLT test. The PLT is
> > requested by Google for evaluating the product's battery life. The
> > product won't be accepted by Google if it fails the PLT test. So we
> > set the ASPM L1 entry delay to 20/21us.
> >
> > With such a short idle period, during 4K reads, the idle time between
> > the read requests will be larger than 20/21us, so GL9763e will enter
> > ASPM L1 very frequently to impact the performance.
> >
> > The bad performance of 4K reads was highlighted by Google, too. Our
> > customer has to pass both the PLT test and 4K read performance test by
> > Google's request. So after some discussions with our customer and
> > Google, we decided to submit such a patch to get the best balance to
> > satisfy Google's requiremnet.
> >
> > The function and the register is vendor specified of GL9763e, so we
> > access it in the vendor driver of GL9763e. Add some functions in other
> > mmc general codes to do something only for GL9763e and can not be
> > applied by other devices might be a little bit strange and difficult
> > to implement and design?
>
> I haven't said implementation need to be easy, but suggest a few
> options to move forward.
>
> What did state and I am not going to change my opinion on this, is the
> governor code that monitors for use cases, don't belong in the driver.
>

Hi Ulf,


Thanks, I understand what you mean.

I simply searched for the keyword "MMC_READ_MULTIPLE_BLOCK" in the
drivers/mmc/host folder, and found that in some SD/MMC host controller
driver codes such as alcor.c, cavium.c, ...etc, there are also
behaviors for monitoring the request in their driver. What's the
difference between theirs and ours?

And if the code that monitors the requstes does not belong the driver,
where should I implement the code and how to add some functions only
for GL9763e in that place, in your opinion?

Thanks for clarifying my questions.


Best regards,

Renius

> Kind regards
> Uffe

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