lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAEUhbmWXO+kHTmQEggjcyyqpQaLwVFeu2ueos+a4WN=P34Vwrg@mail.gmail.com>
Date:   Thu, 8 Jul 2021 21:39:40 +0800
From:   Bin Meng <bmeng.cn@...il.com>
To:     Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Atish Patra <atish.patra@....com>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>
Cc:     Bin Meng <bin.meng@...driver.com>
Subject: Re: [PATCH] riscv: dts: microchip: Define hart clocks

On Wed, Jun 16, 2021 at 2:27 PM Bin Meng <bmeng.cn@...il.com> wrote:
>
> From: Bin Meng <bin.meng@...driver.com>
>
> Declare that each hart in the DT is clocked by <&clkcfg 0>.
>
> Signed-off-by: Bin Meng <bin.meng@...driver.com>
>
> ---
> Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
> this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
> calculate the running frequency of the hart.
>
>  arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
>

Ping?

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ