lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 8 Jul 2021 23:11:43 +0000
From:   "Ismail, Mohammad Athari" <mohammad.athari.ismail@...el.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     Heiner Kallweit <hkallweit1@...il.com>,
        "David S . Miller" <davem@...emloft.net>,
        Russell King <linux@...linux.org.uk>,
        Jakub Kicinski <kuba@...nel.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net] net: phy: reconfigure PHY WOL in resume if WOL option
 still enabled



> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Thursday, July 8, 2021 9:11 PM
> To: Ismail, Mohammad Athari <mohammad.athari.ismail@...el.com>
> Cc: Heiner Kallweit <hkallweit1@...il.com>; David S . Miller
> <davem@...emloft.net>; Russell King <linux@...linux.org.uk>; Jakub
> Kicinski <kuba@...nel.org>; Florian Fainelli <f.fainelli@...il.com>;
> netdev@...r.kernel.org; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH net] net: phy: reconfigure PHY WOL in resume if WOL
> option still enabled
> 
> > Hi Andrew,
> >
> > In our platform, the PHY interrupt pin is not connected to Host CPU. So, the
> CPU couldn`t service the PHY interrupt.  The PHY interrupt pin is connected to
> a power management controller (PMC) as a HW wake up signal. The PMC
> itself couldn't act as interrupt controller to service the PHY interrupt.
> >
> > During WOL event, the WOL signal is sent to PMC through the PHY interrupt
> pin to wake up the PMC. Then, the PMC will wake up the Host CPU and the
> whole system.
> 
> How is the PMC connected to the host? LPC? At wake up can you ask it why it
> woke you up? What event it was, power restored, power button press, or
> WOL? Can the PMC generate interrupts over the LPC? What PMC is it? Is
> there a datasheet for it?
> 
> Getting your architecture correct will also solve your S3/S4 problems.

Hi Andrew,

I'll try to get more info from our architecture design team.

-Athari-

> 
>     Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ