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Message-ID: <CAE-0n51btkt9ehEFrm+WucP90ZufKw1PEQqzNGVDRy51jByXkw@mail.gmail.com>
Date: Thu, 8 Jul 2021 23:22:54 +0000
From: Stephen Boyd <swboyd@...omium.org>
To: Andy Gross <agross@...nel.org>, Georgi Djakov <djakov@...nel.org>,
Odelu Kukatla <okukatla@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>,
Sibi Sankar <sibis@...eaurora.org>, bjorn.andersson@...aro.org,
devicetree@...r.kernel.org, evgreen@...gle.com,
georgi.djakov@...aro.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org
Cc: seansw@....qualcomm.com, elder@...aro.org,
linux-arm-msm-owner@...r.kernel.org
Subject: Re: [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
Quoting Odelu Kukatla (2021-06-18 04:28:52)
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@...eaurora.org>
> ---
> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++-
> include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++-
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index d6a95c3..9f67c8e 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -18,12 +18,19 @@ properties:
> compatible:
> enum:
> - qcom,sc7180-osm-l3
> + - qcom,sc7280-epss-l3
> - qcom,sdm845-osm-l3
> - qcom,sm8150-osm-l3
> - qcom,sm8250-epss-l3
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
Can we base this on the compatible string so that only sc7280-epss-l3
requires 4 items? and then the others require 1 reg property?
> + items:
> + - description: OSM clock domain-0 base address and size
> + - description: OSM clock domain-1 base address and size
> + - description: OSM clock domain-2 base address and size
> + - description: OSM clock domain-3 base address and size
>
> clocks:
> items:
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