linux-kernel - [PATCH 1/1] ARM: dts: qcom: sdx65: Add pincontrol node

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Message-ID: <20210709200819.20373-2-quic_vamslank@quicinc.com>
Date:   Fri, 9 Jul 2021 13:08:19 -0700
From:   <quic_vamslank@...cinc.com>
To:     <agross@...nel.org>, <robh+dt@...nel.org>,
        <bjorn.andersson@...aro.org>, <linus.walleij@...aro.org>
CC:     <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <manivannan.sadhasivam@...aro.org>,
        "Vamsi krishna Lanka" <quic_vamslank@...cinc.com>
Subject: [PATCH 1/1] ARM: dts: qcom: sdx65: Add pincontrol node

From: Vamsi krishna Lanka <quic_vamslank@...cinc.com>

This commit adds pincontrol node to SDX65 dts.

Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@...cinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 4b5e7248c34d..155635d1de2f 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -96,6 +96,17 @@ blsp1_uart3: serial@...000 {
 			status = "disabled";
 		};
 
+		tlmm: pinctrl@...0000 {
+			compatible = "qcom,sdx65-pinctrl";
+			reg = <0xf100000 0x300000>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+		};
+
 		pdc: interrupt-controller@...0000 {
 			compatible = "qcom,sdx65-pdc", "qcom,pdc";
 			reg = <0xb210000 0x10000>;
-- 
2.32.0