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Message-ID: <20210713125743.1540-3-a-nandan@ti.com>
Date: Tue, 13 Jul 2021 12:57:42 +0000
From: Apurva Nandan <a-nandan@...com>
To: Mark Brown <broonie@...nel.org>, <linux-spi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: Apurva Nandan <a-nandan@...com>, Pratyush Yadav <p.yadav@...com>,
Vignesh Raghavendra <vigneshr@...com>
Subject: [PATCH 2/2] spi: cadence-quadspi: Fix check condition for DTR ops
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.
Fix the dtr checks in set_protocol() and suppports_mem_op() to
ignore empty spi_mem_op phases, as checking for dtr field in
empty phase will result in false negatives.
Signed-off-by: Apurva Nandan <a-nandan@...com>
---
drivers/spi/spi-cadence-quadspi.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a2e1f4ce8b3e..a884678e8dff 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -322,7 +322,9 @@ static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
- f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
+ f_pdata->dtr = op->cmd.dtr &&
+ (op->addr.dtr || !op->addr.nbytes) &&
+ (op->data.dtr || !op->data.nbytes);
switch (op->data.buswidth) {
case 0:
@@ -1225,8 +1227,12 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem,
{
bool all_true, all_false;
- all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
- op->data.dtr;
+ /* op->dummy.dtr is checked when converting nbytes into ncycles.*/
+ all_true = op->cmd.dtr &&
+ (op->addr.dtr || !op->addr.nbytes) &&
+ (op->dummy.dtr || !op->dummy.nbytes) &&
+ (op->data.dtr || !op->data.nbytes);
+
all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
!op->data.dtr;
--
2.17.1
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