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Message-ID: <fab62613-59a4-5d0b-4ff8-3900ef70a49d@foss.st.com>
Date: Tue, 13 Jul 2021 18:47:44 +0200
From: Philippe CORNU <philippe.cornu@...s.st.com>
To: Antonio Borneo <antonio.borneo@...s.st.com>,
Yannick Fertre <yannick.fertre@...s.st.com>,
Benjamin Gaignard <benjamin.gaignard@...aro.org>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Raphael Gallais-Pou <raphael.gallais-pou@...s.st.com>,
<dri-devel@...ts.freedesktop.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>
CC: <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/stm: dsi: compute the transition time from LP to HS
and back
Hi Antonio,
On 7/13/21 4:49 PM, Antonio Borneo wrote:
> The driver uses a conservative set of hardcoded values for the
> maximum time delay of the transitions between LP and HS, either
> for data and clock lanes.
>
> By using the info in STM32MP157 datasheet, valid also for other ST
> devices, compute the actual delay from the lane's bps.
>
> Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
> ---
> To: Yannick Fertre <yannick.fertre@...s.st.com>
> To: Philippe Cornu <philippe.cornu@...s.st.com>
> To: Benjamin Gaignard <benjamin.gaignard@...aro.org>
> To: David Airlie <airlied@...ux.ie>
> To: Daniel Vetter <daniel@...ll.ch>
> To: Maxime Coquelin <mcoquelin.stm32@...il.com>
> To: Alexandre Torgue <alexandre.torgue@...s.st.com>
> To: Raphael Gallais-Pou <raphael.gallais-pou@...s.st.com>
> To: dri-devel@...ts.freedesktop.org
> To: linux-stm32@...md-mailman.stormreply.com
> To: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
>
> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> index 8399d337589d..32cb41b2202f 100644
> --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> @@ -309,14 +309,23 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> return 0;
> }
>
> +#define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)
> +
> static int
> dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> struct dw_mipi_dsi_dphy_timing *timing)
> {
> - timing->clk_hs2lp = 0x40;
> - timing->clk_lp2hs = 0x40;
> - timing->data_hs2lp = 0x40;
> - timing->data_lp2hs = 0x40;
> + /*
> + * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747
> + * phy_clkhs2lp_time = (272+136*UI)/(8*UI)
> + * phy_clklp2hs_time = (512+40*UI)/(8*UI)
> + * phy_hs2lp_time = (192+64*UI)/(8*UI)
> + * phy_lp2hs_time = (256+32*UI)/(8*UI)
> + */
> + timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
> + timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
> + timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
> + timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
Many thanks for your patch.
Reviewed-by: Philippe Cornu <philippe.cornu@...s.st.com>
Acked-by: Philippe Cornu <philippe.cornu@...s.st.com>
I will apply it on drm-misc-next early next week,
Philippe :-)
>
> return 0;
> }
>
> base-commit: 35d283658a6196b2057be562096610c6793e1219
>
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