| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20210714194036.53141-14-sashal@kernel.org>
Date: Wed, 14 Jul 2021 15:39:07 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: Elaine Zhang <zhangqing@...k-chips.com>,
Enric Balletbo i Serra <enric.balletbo@...labora.com>,
Johan Jonker <jbx6244@...il.com>,
Heiko Stuebner <heiko@...ech.de>,
Sasha Levin <sashal@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org
Subject: [PATCH AUTOSEL 5.12 014/102] arm64: dts: rockchip: Fix power-controller node names for rk3399
From: Elaine Zhang <zhangqing@...k-chips.com>
[ Upstream commit 148bbe29f9108812c6fedd8a228f9e1ed6b422f7 ]
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
Signed-off-by: Johan Jonker <jbx6244@...il.com>
Link: https://lore.kernel.org/r/20210417112952.8516-8-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 02e8d9b5174d..b265cc1b558d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -971,26 +971,26 @@ power: power-controller {
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
- pd_iep@...399_PD_IEP {
+ power-domain@...399_PD_IEP {
reg = <RK3399_PD_IEP>;
clocks = <&cru ACLK_IEP>,
<&cru HCLK_IEP>;
pm_qos = <&qos_iep>;
};
- pd_rga@...399_PD_RGA {
+ power-domain@...399_PD_RGA {
reg = <RK3399_PD_RGA>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_rga_r>,
<&qos_rga_w>;
};
- pd_vcodec@...399_PD_VCODEC {
+ power-domain@...399_PD_VCODEC {
reg = <RK3399_PD_VCODEC>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video_m0>;
};
- pd_vdu@...399_PD_VDU {
+ power-domain@...399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
@@ -999,94 +999,94 @@ pd_vdu@...399_PD_VDU {
};
/* These power domains are grouped by VD_GPU */
- pd_gpu@...399_PD_GPU {
+ power-domain@...399_PD_GPU {
reg = <RK3399_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
/* These power domains are grouped by VD_LOGIC */
- pd_edp@...399_PD_EDP {
+ power-domain@...399_PD_EDP {
reg = <RK3399_PD_EDP>;
clocks = <&cru PCLK_EDP_CTRL>;
};
- pd_emmc@...399_PD_EMMC {
+ power-domain@...399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
pm_qos = <&qos_emmc>;
};
- pd_gmac@...399_PD_GMAC {
+ power-domain@...399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
};
- pd_sd@...399_PD_SD {
+ power-domain@...399_PD_SD {
reg = <RK3399_PD_SD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
};
- pd_sdioaudio@...399_PD_SDIOAUDIO {
+ power-domain@...399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
clocks = <&cru HCLK_SDIO>;
pm_qos = <&qos_sdioaudio>;
};
- pd_tcpc0@...399_PD_TCPD0 {
+ power-domain@...399_PD_TCPD0 {
reg = <RK3399_PD_TCPD0>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
};
- pd_tcpc1@...399_PD_TCPD1 {
+ power-domain@...399_PD_TCPD1 {
reg = <RK3399_PD_TCPD1>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
};
- pd_usb3@...399_PD_USB3 {
+ power-domain@...399_PD_USB3 {
reg = <RK3399_PD_USB3>;
clocks = <&cru ACLK_USB3>;
pm_qos = <&qos_usb_otg0>,
<&qos_usb_otg1>;
};
- pd_vio@...399_PD_VIO {
+ power-domain@...399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
#size-cells = <0>;
- pd_hdcp@...399_PD_HDCP {
+ power-domain@...399_PD_HDCP {
reg = <RK3399_PD_HDCP>;
clocks = <&cru ACLK_HDCP>,
<&cru HCLK_HDCP>,
<&cru PCLK_HDCP>;
pm_qos = <&qos_hdcp>;
};
- pd_isp0@...399_PD_ISP0 {
+ power-domain@...399_PD_ISP0 {
reg = <RK3399_PD_ISP0>;
clocks = <&cru ACLK_ISP0>,
<&cru HCLK_ISP0>;
pm_qos = <&qos_isp0_m0>,
<&qos_isp0_m1>;
};
- pd_isp1@...399_PD_ISP1 {
+ power-domain@...399_PD_ISP1 {
reg = <RK3399_PD_ISP1>;
clocks = <&cru ACLK_ISP1>,
<&cru HCLK_ISP1>;
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
};
- pd_vo@...399_PD_VO {
+ power-domain@...399_PD_VO {
reg = <RK3399_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
- pd_vopb@...399_PD_VOPB {
+ power-domain@...399_PD_VOPB {
reg = <RK3399_PD_VOPB>;
clocks = <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>;
pm_qos = <&qos_vop_big_r>,
<&qos_vop_big_w>;
};
- pd_vopl@...399_PD_VOPL {
+ power-domain@...399_PD_VOPL {
reg = <RK3399_PD_VOPL>;
clocks = <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
--
2.30.2
Powered by blists - more mailing lists