lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 13 Jul 2021 19:58:49 -0600 From: Rob Herring <robh@...nel.org> To: Christine Zhu <Christine.Zhu@...iatek.com> Cc: wim@...ux-watchdog.org, linux@...ck-us.net, matthias.bgg@...il.com, srv_heupstream@...iatek.com, linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org, seiya.wang@...iatek.com Subject: Re: [v5,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file On Mon, Jun 28, 2021 at 07:37:30PM +0800, Christine Zhu wrote: > From: "Christine Zhu" <Christine.Zhu@...iatek.com> > > Add toprgu reset-controller head file for MT8195 platform. s/head/header/ And the subject too. > > Signed-off-by: Christine Zhu <Christine.Zhu@...iatek.com> > --- > .../reset-controller/mt8195-resets.h | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h > new file mode 100644 > index 000000000000..7ec27a64afc7 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt8195-resets.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. > +/* > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Crystal Guo <crystal.guo@...iatek.com> According to the S-o-b and patch author, you are the author. > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 > + > +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 > +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 > +#define MT8195_TOPRGU_APU_SW_RST 2 > +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 > +#define MT8195_TOPRGU_MMSYS_SW_RST 7 > +#define MT8195_TOPRGU_MFG_SW_RST 8 > +#define MT8195_TOPRGU_VENC_SW_RST 9 > +#define MT8195_TOPRGU_VDEC_SW_RST 10 > +#define MT8195_TOPRGU_IMG_SW_RST 11 > +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 > +#define MT8195_TOPRGU_AUDIO_SW_RST 14 > +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 > +#define MT8195_TOPRGU_EDPTX_SW_RST 16 > +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 > +#define MT8195_TOPRGU_DPTX_SW_RST 22 > +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 > + > +#define MT8195_TOPRGU_SW_RST_NUM 16 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ > -- > 2.18.0 > >
Powered by blists - more mailing lists