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Message-ID: <1626316157-24935-4-git-send-email-kewei.xu@mediatek.com>
Date: Thu, 15 Jul 2021 10:29:12 +0800
From: Kewei Xu <kewei.xu@...iatek.com>
To: <wsa@...-dreams.de>
CC: <matthias.bgg@...il.com>, <robh+dt@...nel.org>,
<linux-i2c@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>, <leilk.liu@...iatek.com>,
<qii.wang@...iatek.com>, <qiangming.xia@...iatek.com>,
<kewei.xu@...iatek.com>, <ot_daolong.zhu@...iatek.com>
Subject: [PATCH 3/8] i2c: mediatek: fixing the incorrect register offset
The reason for the modification here is that the previous
offset information is incorrect, OFFSET_DEBUGSTAT = 0xE4 is
the correct value.
Signed-off-by: Kewei Xu <kewei.xu@...iatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 64acd96..e65a41e 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -195,7 +195,7 @@ enum I2C_REGS_OFFSET {
[OFFSET_SOFTRESET] = 0x50,
[OFFSET_MULTI_DMA] = 0x84,
[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
- [OFFSET_DEBUGSTAT] = 0xe0,
+ [OFFSET_DEBUGSTAT] = 0xe4,
[OFFSET_DEBUGCTRL] = 0xe8,
[OFFSET_FIFO_STAT] = 0xf4,
[OFFSET_FIFO_THRESH] = 0xf8,
--
1.9.1
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