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Message-ID: <29bf6fa3-b23c-c646-b8fa-44580a4e404b@gmail.com>
Date: Thu, 15 Jul 2021 11:06:44 +0800
From: Like Xu <like.xu.linux@...il.com>
To: Jin Yao <yao.jin@...ux.intel.com>
Cc: Linux-kernel@...r.kernel.org, ak@...ux.intel.com,
kan.liang@...el.com, yao.jin@...el.com, acme@...nel.org,
mingo@...hat.com,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
jolsa@...nel.org, Peter Zijlstra <peterz@...radead.org>
Subject: Re: [PATCH 1/2] perf vendor events intel: Add core event list for
Elkhartlake
On 6/7/2021 2:00 pm, Jin Yao wrote:
> Add JSON core events for Elkhartlake to perf.
>
> Based on JSON list v1.01:
>
> https://download.01.org/perfmon/EHL/
>
> Signed-off-by: Jin Yao <yao.jin@...ux.intel.com>
> ---
> .../arch/x86/elkhartlake/cache.json | 227 +++++++++++++
> .../arch/x86/elkhartlake/floating-point.json | 13 +
> .../arch/x86/elkhartlake/frontend.json | 26 ++
> .../arch/x86/elkhartlake/memory.json | 74 +++++
> .../arch/x86/elkhartlake/other.json | 302 ++++++++++++++++++
> .../arch/x86/elkhartlake/pipeline.json | 135 ++++++++
> .../arch/x86/elkhartlake/virtual-memory.json | 86 +++++
> tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
> 8 files changed, 864 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
>
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
> new file mode 100644
> index 000000000000..5ccca7bf4a90
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
> @@ -0,0 +1,227 @@
> +[
> + {
> + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x2e",
> + "EventName": "LONGEST_LAT_CACHE.ANY",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4f"
> + },
> + {
> + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x2e",
> + "EventName": "LONGEST_LAT_CACHE.MISS",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x41"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event LONGEST_LAT_CACHE.ANY",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x2e",
> + "EventName": "LONGEST_LAT_CACHE.REFERENCE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4f"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).",
> + "SampleAfterValue": "200003",
> + "UMask": "0x20"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of cycles a core is stalled due to a store buffer being full.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x40"
> + },
> + {
> + "BriefDescription": "Counts the number of load ops retired that hit in DRAM.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "Errata": "https://hsdes.intel.com/appstore/article/#/1707187406",
Seriously, for this url ?
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x80"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xd1",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of load uops retired.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd0",
> + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of load uops retired.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x81"
> + },
> + {
> + "BriefDescription": "Counts the number of store uops retired.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "Data_LA": "1",
> + "EventCode": "0xd0",
> + "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of store uops retired.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x82"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.ICACHE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x20"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
> new file mode 100644
> index 000000000000..21d85ba3266f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
> @@ -0,0 +1,13 @@
> +[
> + {
> + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc2",
> + "EventName": "UOPS_RETIRED.FPDIV",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x8"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
> new file mode 100644
> index 000000000000..e53f4ff2b758
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
> @@ -0,0 +1,26 @@
> +[
> + {
> + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x80",
> + "EventName": "ICACHE.ACCESSES",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x3"
> + },
> + {
> + "BriefDescription": "Counts the number of instruction cache misses.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x80",
> + "EventName": "ICACHE.MISSES",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x2"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
> new file mode 100644
> index 000000000000..7c427047baad
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
> @@ -0,0 +1,74 @@
> +[
> + {
> + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F04000001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2104000001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F04000001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2104000001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_RFO.L3_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F04000002",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2104000002",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> new file mode 100644
> index 000000000000..f999b89297ab
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> @@ -0,0 +1,302 @@
> +[
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "C0_STALLS.LOAD_DRAM_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "C0_STALLS.LOAD_L2_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x34",
> + "EventName": "C0_STALLS.LOAD_LLC_HIT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "200003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0XB7",
> + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10002",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x6"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.REGISTER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x20"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x40"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "This event is deprecated.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x40"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.CISC",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.DECODE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.ITLB",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.OTHER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x80"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the total number of consumed retirement slots.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc2",
> + "EventName": "TOPDOWN_RETIRING.ALL",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> new file mode 100644
> index 000000000000..988708f50603
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> @@ -0,0 +1,135 @@
> +[
> + {
> + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc4",
> + "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
> + "SampleAfterValue": "200003"
> + },
> + {
> + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc5",
> + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
> + "SampleAfterValue": "200003"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
> + "CollectPEBSRecord": "2",
> + "Counter": "33",
> + "EventName": "CPU_CLK_UNHALTED.CORE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "33",
> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted core clock cycles.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x3c",
> + "EventName": "CPU_CLK_UNHALTED.CORE_P",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
> + "SampleAfterValue": "2000003"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x3c",
> + "EventName": "CPU_CLK_UNHALTED.REF",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
> + "CollectPEBSRecord": "2",
> + "Counter": "34",
> + "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "34",
> + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x3"
> + },
> + {
> + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x3c",
> + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "This event is deprecated.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xcd",
> + "EventName": "CYCLES_DIV_BUSY.ANY",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "2000003"
> + },
> + {
> + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
> + "CollectPEBSRecord": "2",
> + "Counter": "32",
> + "EventName": "INST_RETIRED.ANY",
> + "PEBS": "1",
> + "PEBScounters": "32",
> + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the total number of instructions retired.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc0",
> + "EventName": "INST_RETIRED.ANY_P",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
> + "SampleAfterValue": "2000003"
> + },
> + {
> + "BriefDescription": "Counts the total number of machine clears including memory ordering, memory disambiguation, self-modifying code, page faults and floating point assist.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc3",
> + "EventName": "MACHINE_CLEARS.ANY",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "20003"
> + },
> + {
> + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc2",
> + "EventName": "UOPS_RETIRED.MS",
> + "PDIR_COUNTER": "na",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
> new file mode 100644
> index 000000000000..246df2fe737b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
> @@ -0,0 +1,86 @@
> +[
> + {
> + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x08",
> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x08",
> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x49",
> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x49",
> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x81",
> + "EventName": "ITLB.FILLS",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
> + "SampleAfterValue": "200003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x85",
> + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x85",
> + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
> index 5f5df6560202..64719168ab0a 100644
> --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> @@ -41,6 +41,7 @@ GenuineIntel-6-A7,v1,icelake,core
> GenuineIntel-6-6A,v1,icelakex,core
> GenuineIntel-6-6C,v1,icelakex,core
> GenuineIntel-6-86,v1,tremontx,core
> +GenuineIntel-6-96,v1,elkhartlake,core
> AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
> AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core
> AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core
>
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