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Message-ID: <73e1e3a2-c2dd-364b-7829-84e66b114909@gmail.com>
Date: Thu, 15 Jul 2021 18:36:31 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: Thierry Reding <treding@...dia.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Mark Brown <broonie@...nel.org>,
Sebastian Reichel <sre@...nel.org>,
Peter Chen <peter.chen@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Felipe Balbi <balbi@...nel.org>,
David Heidelberg <david@...t.cz>, devicetree@...r.kernel.org,
linux-pm@...r.kernel.org, linux-usb@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: Re: [PATCH v3 02/12] dt-bindings: phy: tegra20-usb-phy: Document
properties needed for OTG mode
15.07.2021 02:10, Rob Herring пишет:
> On Tue, Jul 13, 2021 at 02:33:11AM +0300, Dmitry Osipenko wrote:
>> 12.07.2021 18:41, Rob Herring пишет:
>>>> + nvidia,pmc:
>>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>>> + description:
>>>> + Phandle to Power Management controller.
>>>> +
>>> Add a cell to this for the PHY reg offset and then get rid of the index:
>>>
>>>> + nvidia,phy-instance:
>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>> + minimum: 0
>>>> + maximum: 2
>>>> + description: Unique hardware ID.
>>
>> The instance ID belongs to the USB h/w and not to PMC. It may look like
>> I added the ID just to get offsets within PMC, but it's not like that.
>> The Tegra documentation explicitly assigns unique IDs to the USB
>> controllers and PHYs. Hence this ID should be the property of the PHY
>> hardware, IMO.
>
> It looks like the use is calculating register offsets in a PMC register.
> That's quite common and including that with the phandle is the preferred
> way to describe it.
>
> Lots of docs have UART1, UART2, UART3, etc. module numbering. We don't
> copy that into DT.
Alright. Judging by downstream code, we will need to use that ID only
for PMC offsets.
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