Message-ID: <CAFBinCAohjxcsY3D1rdAiYVGL+==cnjzZxg1GmYxSNVhxSTDoA@mail.gmail.com>
Date:   Sun, 18 Jul 2021 21:09:36 +0200
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     Anand Moon <linux.amoon@...il.com>
Cc:     linux-phy@...ts.infradead.org,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-amlogic@...ts.infradead.org,
        Linux Kernel <linux-kernel@...r.kernel.org>,
        Matt Corallo <oc2udbzfd@...tcorallo.com>,
        Rob Herring <robh+dt@...nel.org>,
        Neil Armstrong <narmstrong@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Emiliano Ingrassia <ingrassia@...genesys.com>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCHv2 1/4] ARM: dts: meson8b: odroidc1: Add usb phy power node

Hi Anand,

On Sun, Jul 18, 2021 at 4:01 PM Martin Blumenstingl
<martin.blumenstingl@...glemail.com> wrote:
[...]
> > From the schematics [1]
> > https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf
> >
> > You could find references to PWREN  <--- GPIOAO.BIT5
> > The second reference is USB HOST Power Switch
> > The third reference is USB HOST POWER.
> >
> > Hope I am clean in my thought process now.
> Can you please point out the page numbers for me?
>
> What I am seeing on page 1 is:
> GPIOAO_5 (called GPIOAO.BIT5) is connected as an INPUT to the USB_OTG
> PWREN signal (that's the green box with the label "USB_OTG.SchDoc"
> above it).
I unfortunately missed your question on IRC on this topic:
<armoon> xdarklight: just want to understand the confusion on PWREN,
either is INPUT / OTPUT to usb hub am I correct
My understanding of the INPUT/OUTPUT direction in the Odroid-C1
schematics (which you linked) above is that the arrow direction shows
whether it's an input or output.
For example (all on page one):
- HDMI_HPD is an input to the Meson8b SoC, arrow direction is: HDMI => S805
- IR_IN is an input to the Meson8b SoC, arrow direction is: S805 <=
GPIOAO.BIT7 IR_IN
- PWM is an output, arrow direction is: S805 => PWM.C VCCK_PWM
- 3.3V/1.8V switch for the SD card is an output, arrow direction is:
S805 => GPIOAO.BIT3 TF_3V3N_1V8_EN

That tells me: the arrow direction shows which connections are inputs
or outputs.
Some pins can be input and output at the same time (HDMI_CEC). But
let's keep it simple for now any only look at inputs/output.

Based on this information I am looking at the arrow direction for
USB_OTG: GPIOAO.BIT5 PWREN <= S805
So this confirms that GPIOAO_5 is an output to the SoC.
Please note though that this part is not linked with any USB host
connector, it's only linked to the USB OTG path.

For the next part the S805 SoC is not involved:
USB1 USB_HOST_PWR_SW PWREN <= PWREN USB_HUB_GL852G
USB2 USB_HOST_PWR_SW PWREN <= PWREN USB_HUB_GL852G
This tells me that the PWREN signal for the two USB_HOST_PWR_SW (USB
host power switches / current limiters) is driven by the GL852G USB
hub.

The GL852G USB hub datasheet [0] mentions on page 14:
pin name: PWREN1#~4
I/O type: O (which stands for: OUTPUT)
description: Active low. Power enable output for DSPORT1~4 PWREN1# is
the only power-enable output for GANG mode.
This seems to confirm my understanding of the Odroid-C1 schematics,
where the PWREN signal of the current limiters is coming from the USB
hub (so the Meson8b SoC is not involved directly).

<armoon> sorry I am not the expert in schematics interpretation, but
what I understand is PWREN (GPIOAO.BIT5) is input signal to
MP62551DGT-LF-Z which controls the VBUS signal power to USB HUB to pin
V5 on GL852G IC
That part is unfortunately hard to say because the author of the
Odroid-C1 schematics decided to two different signals called PWREN.
Now it's not clear if this refers to the USB_OTG PWREN or USB_HOST
PWREN signal.
Based on page 1 I *assume* that it's linked to the USB_HOST PWREN signal.

<armoon> plz check the GL852G power section.        it has 5V Power
input. It need be NC if using external regulator
<armoon> 5V and V33 are the regulator for GL852G IC HUB,
Looking at page 27 of the Odroid-C1 schematics I can see that PSELF,
PGANG, V33, AVDD1, AVDD2, AVDD3 and DVDD are supplied by a 3.3V power
supply called HUB_AVDD.
V5 is a 5V signal which is not connected (there's a red cross next to it).

<armoon> I feel setting GPIOAO.BIT5 setting to Active Low just enable
the 5V via external regulator MP62551DGT-LF-Z
My understanding is that GPIOAO.BIT5 enables or disables VBUS for the
USB_OTG port (&usb1 in our .dts)
See page 28 of the schematics, the RT9715EGB power switch uses a PWREN
signal for it's ENABLE pin based on page 1 of the schematics.
MP62551DGT-LF-Z would then be getting it's PWREN signal from the GL852G hub.

Having different power switches for USB HOST and USB OTG makes sense
because for USB OTG the VBUS signal needs to be disabled when in
peripheral/device mode (for example when connecting the Odroid-C1 via
micro-USB cable to a computer).

<armoon> I don't know much on internal IC signal apart from this, may
be I need to check with the board designer Odroid / Hardkernel for
more details
That would be great actually. Unfortunately Brian Kim's email address
(which you had Cc'ed in the beginning of this conversation) is not
valid anymore.
If you have any other contact at Hardkernel then it would be great if
you could add them to the loop so they can clear our questions.


Best regards,
Martin


[0] https://datasheet.lcsc.com/szlcsc/Genesys-Logic-GL852G-HHG12_C136618.pdf

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