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Message-ID: <20210719085402.28569-4-lokeshvutla@ti.com>
Date: Mon, 19 Jul 2021 14:24:01 +0530
From: Lokesh Vutla <lokeshvutla@...com>
To: Nishanth Menon <nm@...com>, <kristo@...nel.org>
CC: Device Tree Mailing List <devicetree@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
Linux ARM Mailing List <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, Lokesh Vutla <lokeshvutla@...com>
Subject: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
signal connected to Pin 1 of J3. Add support for adding this pinmux so
that pwm can be observed on pin 1 of Header J3
Signed-off-by: Lokesh Vutla <lokeshvutla@...com>
Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index d3aa2901e6fd..eb0d10e6e787 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
+
+ main_ecap0_pins_default: main-ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+ >;
+ };
};
&mcu_uart0 {
@@ -453,3 +459,9 @@ &pcie0_rc {
&pcie0_ep {
status = "disabled";
};
+
+&ecap0 {
+ /* PWM is available on Pin 1 of header J3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ecap0_pins_default>;
+};
--
2.30.0
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