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Message-Id: <8c29c4832ed8c44b0c62c79d34b3b5b73603f388.1626743758.git.ming.qian@nxp.com>
Date: Tue, 20 Jul 2021 09:43:30 +0800
From: Ming Qian <ming.qian@....com>
To: mchehab@...nel.org, shawnguo@...nel.org, robh+dt@...nel.org,
s.hauer@...gutronix.de
Cc: hverkuil-cisco@...all.nl, kernel@...gutronix.de,
festevam@...il.com, linux-imx@....com, aisheng.dong@....com,
linux-media@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v4 11/13] ARM64: dts: freescale: imx8q: add imx vpu codec entries
Add the Video Processing Unit node for IMX8Q SoC.
Signed-off-by: Ming Qian <ming.qian@....com>
Signed-off-by: Shijie Qin <shijie.qin@....com>
Signed-off-by: Zhou Peng <eagle.zhou@....com>
---
.../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +++++++
3 files changed, 115 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
new file mode 100644
index 000000000000..9f43f18d0df8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ * Dong Aisheng <aisheng.dong@....com>
+ */
+
+vpu: vpu@...00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
+ reg = <0 0x2c000000 0 0x1000000>;
+ power-domains = <&pd IMX_SC_R_VPU>;
+ status = "disabled";
+
+ mu_m0: mailbox@...00000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d000000 0x20000>;
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_0>;
+ status = "okay";
+ };
+
+ mu1_m0: mailbox@...20000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d020000 0x20000>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_1>;
+ status = "okay";
+ };
+
+ mu2_m0: mailbox@...40000 {
+ compatible = "fsl,imx6sx-mu";
+ reg = <0x2d040000 0x20000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_VPU_MU_2>;
+ status = "disabled";
+ };
+
+ vpu_core0: vpu_core@...80000 {
+ reg = <0x2d080000 0x10000>;
+ compatible = "nxp,imx8q-vpu-decoder";
+ power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu_m0 0 0
+ &mu_m0 0 1
+ &mu_m0 1 0>;
+ status = "disabled";
+ };
+ vpu_core1: vpu_core@...90000 {
+ reg = <0x2d090000 0x10000>;
+ compatible = "nxp,imx8q-vpu-encoder";
+ power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu1_m0 0 0
+ &mu1_m0 0 1
+ &mu1_m0 1 0>;
+ status = "disabled";
+ };
+ vpu_core2: vpu_core@...a0000 {
+ reg = <0x2d0a0000 0x10000>;
+ compatible = "nxp,imx8q-vpu-encoder";
+ power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
+ mbox-names = "tx0", "tx1", "rx";
+ mboxes = <&mu2_m0 0 0
+ &mu2_m0 0 1
+ &mu2_m0 1 0>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 46437d3c7a04..1a282e63507e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -196,6 +196,23 @@ &usdhc2 {
status = "okay";
};
+&vpu {
+ compatible = "nxp,imx8qxp-vpu";
+ status = "okay";
+};
+
+&vpu_core0 {
+ reg = <0x2d040000 0x10000>;
+ memory-region = <&decoder_boot>, <&decoder_rpc>;
+ status = "okay";
+};
+
+&vpu_core1 {
+ reg = <0x2d050000 0x10000>;
+ memory-region = <&encoder_boot>, <&encoder_rpc>;
+ status = "okay";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..b9540de09a7e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -45,6 +45,9 @@ aliases {
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
+ vpu_core0 = &vpu_core0;
+ vpu_core1 = &vpu_core1;
+ vpu_core2 = &vpu_core2;
};
cpus {
@@ -133,10 +136,30 @@ reserved-memory {
#size-cells = <2>;
ranges;
+ decoder_boot: decoder-boot@...00000 {
+ reg = <0 0x84000000 0 0x2000000>;
+ no-map;
+ };
+
+ encoder_boot: encoder-boot@...00000 {
+ reg = <0 0x86000000 0 0x200000>;
+ no-map;
+ };
+
+ decoder_rpc: decoder-rpc@...2000000 {
+ reg = <0 0x92000000 0 0x100000>;
+ no-map;
+ };
+
dsp_reserved: dsp@...00000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
};
+
+ encoder_rpc: encoder-rpc@...4400000 {
+ reg = <0 0x94400000 0 0x700000>;
+ no-map;
+ };
};
pmu {
@@ -629,4 +652,7 @@ map0 {
};
};
};
+
+ /* sorted in register address */
+ #include "imx8-ss-vpu.dtsi"
};
--
2.32.0
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