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Message-ID: <994051df-73b3-4dad-76aa-1a03d9afaf6d@linux.ibm.com>
Date: Wed, 21 Jul 2021 17:04:34 +0200
From: Frederic Barrat <fbarrat@...ux.ibm.com>
To: Alexey Kardashevskiy <aik@...abs.ru>,
Leonardo Bras <leobras.c@...il.com>,
Michael Ellerman <mpe@...erman.id.au>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
David Gibson <david@...son.dropbear.id.au>,
kernel test robot <lkp@...el.com>,
Nicolin Chen <nicoleotsuka@...il.com>
Cc: linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 10/11] powerpc/pseries/iommu: Make use of DDW for
indirect mapping
On 21/07/2021 05:32, Alexey Kardashevskiy wrote:
>>> + struct iommu_table *newtbl;
>>> + int i;
>>> +
>>> + for (i = 0; i < ARRAY_SIZE(pci->phb->mem_resources); i++) {
>>> + const unsigned long mask = IORESOURCE_MEM_64 |
>>> IORESOURCE_MEM;
>>> +
>>> + /* Look for MMIO32 */
>>> + if ((pci->phb->mem_resources[i].flags & mask) ==
>>> IORESOURCE_MEM)
>>> + break;
>>> + }
>>> +
>>> + if (i == ARRAY_SIZE(pci->phb->mem_resources))
>>> + goto out_del_list;
>>
>>
>> So we exit and do nothing if there's no MMIO32 bar?
>> Isn't the intent just to figure out the MMIO32 area to reserve it when
>> init'ing the table? In which case we could default to 0,0
>>
>> I'm actually not clear why we are reserving this area on pseries.
>
>
>
> If we do not reserve it, then the iommu code will allocate DMA pages
> from there and these addresses are MMIO32 from the kernel pov at least.
> I saw crashes when (I think) a device tried DMAing to the top 2GB of the
> bus space which happened to be a some other device's BAR.
hmmm... then figuring out the correct range needs more work. We could
have more than one MMIO32 bar. And they don't have to be adjacent. I
don't see that we are reserving any range on the initial table though
(on pseries).
Fred
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