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Date:   Thu, 22 Jul 2021 21:33:56 +0100
From:   Daniel Scally <djrscally@...il.com>
To:     Daniel Scally <djrscally@...il.com>,
        Mauro Carvalho Chehab <mchehab+huawei@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Paul Kocialkowski <paul.kocialkowski@...tlin.com>,
        Ezequiel Garcia <ezequiel@...labora.com>,
        Hans Verkuil <hverkuil-cisco@...all.nl>,
        Yang Li <yang.lee@...ux.alibaba.com>,
        linux-media@...r.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE
        (V4L/DVB)), linux-kernel@...r.kernel.org (open list)
Cc:     Yong Zhi <yong.zhi@...el.com>, Bingbu Cao <bingbu.cao@...el.com>,
        Tianshu Qiu <tian.shu.qiu@...el.com>,
        Colin Ian King <colin.king@...onical.com>,
        laurent.pinchart@...asonboard.com, kieran.bingham@...asonboard.com
Subject: [PATCH 02/13] media: i2c: Fix incorrect value in comment

The PLL configuration defined here sets 72MHz (which is correct), not
80MHz. Correct the comment.

Signed-off-by: Daniel Scally <djrscally@...il.com>
---
 drivers/media/i2c/ov8865.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c
index fe60cda3dea7..2ef146e7e7ef 100644
--- a/drivers/media/i2c/ov8865.c
+++ b/drivers/media/i2c/ov8865.c
@@ -713,7 +713,7 @@ static const struct ov8865_pll2_config ov8865_pll2_config_native = {
 /*
  * EXTCLK = 24 MHz
  * DAC_CLK = 360 MHz
- * SCLK = 80 MHz
+ * SCLK = 72 MHz
  */
 
 static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
-- 
2.25.1

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