linux-kernel - Issues with A3720 PCIe controller driver pci-aardvark.c

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Message-ID: <20210723221710.wtztsrddudnxeoj3@pali>
Date:   Sat, 24 Jul 2021 00:17:10 +0200
From:   Pali Rohár <pali@...nel.org>
To:     Konstantin Porotchkin <kostap@...vell.com>
Cc:     Krzysztof Wilczyński <kw@...ux.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Marek Behún <kabel@...nel.org>,
        Remi Pommarel <repk@...plefau.lt>, Xogium <contact@...ium.me>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Issues with A3720 PCIe controller driver pci-aardvark.c

Hello Konstantin!

There are issues with Marvell Armada 3720 PCIe controller when high
performance PCIe card (e.g. WiFi AX) is connected to this SOC. Under
heavy load PCIe controller sends fatal abort to CPU and kernel crash.

In Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
document is described erratum 3.12 PCIe Completion Timeout (Ref #: 251)
which may be relevant. But neither Bjorn, Thomas nor me were able to
understood text of this erratum. And we have already spent lot of time
on this erratum. My guess that is that in erratum itself are mistakes
and there are missing some other important details.

Konstantin, are you able to understand this erratum? Or do you know
somebody in Marvell who understand this erratum and can explain details
to us? Or do you know some more details about this erratum?

Also it would be useful if you / Marvell could share text of this
erratum with linux-pci people as currently it is available only on
Marvell Customer Portal which requires registration with signed NDA.

In past Thomas wrote patch "according to this erratum" and I have
rebased, rewritten and resent it to linux-pci mailing list for review:
https://lore.kernel.org/linux-pci/20210624222621.4776-6-pali@kernel.org/

Similar patch is available also in kernel which is part of Marvell SDK.

Bjorn has objections for this patch as he thinks that bit DIS_ORD_CHK in
that patch should be disabled. Seems that enabling this bit effectively
disables PCIe strong ordering model. PCIe kernel drivers rely on PCIe
strong ordering, so it would implicate that that bit should not be
enabled. Which is opposite of what is mentioned patch doing.

Konstantin, could you help us with this problem?