linux-kernel - Re: [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible

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Message-ID: <8735s530rx.wl-maz@kernel.org>
Date:   Fri, 23 Jul 2021 09:14:10 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     Bjorn Helgaas <helgaas@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        LKML <linux-kernel@...r.kernel.org>,
        Alex Williamson <alex.williamson@...hat.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Kevin Tian <kevin.tian@...el.com>,
        Ingo Molnar <mingo@...nel.org>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible

On Thu, 22 Jul 2021 22:54:48 +0100,
Andy Shevchenko <andy.shevchenko@...il.com> wrote:
> 
> [1  <text/plain; UTF-8 (7bit)>]
> On Friday, July 23, 2021, Bjorn Helgaas <helgaas@...nel.org> wrote:
> 
> > On Wed, Jul 21, 2021 at 09:11:30PM +0200, Thomas Gleixner wrote:
> > > Nothing enforces the posted writes to be visible when the function
> > > returns. Flush them even if the flush might be redundant when the entry
> > is
> > > masked already as the unmask will flush as well. This is either setup or
> > a
> > > rare affinity change event so the extra flush is not the end of the
> > world.
> > >
> > > While this is more a theoretical issue especially the X86 MSI affinity
> > > stter mechanism relies on the assumption that the update has reached the
> >
> > stter?
> 
> 
> Setter I suppose

My bet is on 'steer', given that this is about affinity management.

	M.

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