linux-kernel - [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file

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Message-ID: <20210723093127.24568-3-Christine.Zhu@mediatek.com>
Date:   Fri, 23 Jul 2021 17:31:27 +0800
From:   Christine Zhu <Christine.Zhu@...iatek.com>
To:     <wim@...ux-watchdog.org>, <linux@...ck-us.net>,
        <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC:     <srv_heupstream@...iatek.com>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-watchdog@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <seiya.wang@...iatek.com>,
        <Rex-BC.Chen@...iatek.com>,
        Christine Zhu <Christine.Zhu@...iatek.com>
Subject: [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file

Add toprgu reset-controller header file for MT8195 platform

Signed-off-by: Christine Zhu <Christine.Zhu@...iatek.com>
---
 .../reset-controller/mt8195-resets.h          | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h

diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h
new file mode 100644
index 000000000000..8176a3e5063f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8195-resets.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either licens
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Christine Zhu <christine.zhu@...iatek.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
+
+#define MT8195_TOPRGU_CONN_MCU_SW_RST          0
+#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
+#define MT8195_TOPRGU_APU_SW_RST               2
+#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST     6
+#define MT8195_TOPRGU_MMSYS_SW_RST             7
+#define MT8195_TOPRGU_MFG_SW_RST               8
+#define MT8195_TOPRGU_VENC_SW_RST              9
+#define MT8195_TOPRGU_VDEC_SW_RST              10
+#define MT8195_TOPRGU_IMG_SW_RST               11
+#define MT8195_TOPRGU_APMIXEDSYS_SW_RST        13
+#define MT8195_TOPRGU_AUDIO_SW_RST             14
+#define MT8195_TOPRGU_CAMSYS_SW_RST            15
+#define MT8195_TOPRGU_EDPTX_SW_RST             16
+#define MT8195_TOPRGU_ADSPSYS_SW_RST           21
+#define MT8195_TOPRGU_DPTX_SW_RST              22
+#define MT8195_TOPRGU_SPMI_MST_SW_RST          23
+
+#define MT8195_TOPRGU_SW_RST_NUM               16
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
-- 
2.18.0