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Date:   Sun, 25 Jul 2021 16:29:12 -0600
From:   Rob Herring <robh+dt@...nel.org>
To:     Atish Patra <atish.patra@....com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Albert Ou <aou@...s.berkeley.edu>,
        Christoph Hellwig <hch@....de>, devicetree@...r.kernel.org,
        Dmitry Vyukov <dvyukov@...gle.com>,
        Frank Rowand <frowand.list@...il.com>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Linux IOMMU <iommu@...ts.linux-foundation.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Robin Murphy <robin.murphy@....com>,
        Tobias Klauser <tklauser@...tanz.ch>
Subject: Re: [RFC 3/5] dma-mapping: Enable global non-coherent pool support
 for RISC-V

On Fri, Jul 23, 2021 at 3:40 PM Atish Patra <atish.patra@....com> wrote:
>
> Currently, linux,dma-default is used to reserve a global non-coherent pool
> to allocate memory for dma operations. This can be useful for RISC-V as
> well as the ISA specification doesn't specify a method to modify PMA
> attributes or page table entries to define non-cacheable area yet.
> A non-cacheable memory window is an alternate options for vendors to
> support non-coherent devices. "dma-ranges" must be used in conjunction with
> "linux,dma-default" property to define one or more mappings between device
> and cpu accesible memory regions.

'dma-ranges' applies to buses. And, well, maybe devices when the bus
is not well defined. It is not a reserved-memory property.

Rob

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