Message-ID: <CAOnJCU+qRznBTn9Mt6t_DE6UUz6_LuaBBuOmnURS2Yh3pmpjvg@mail.gmail.com>
Date:   Mon, 26 Jul 2021 15:47:54 -0700
From:   Atish Patra <atishp@...shpatra.org>
To:     Christoph Hellwig <hch@....de>
Cc:     Atish Patra <atish.patra@....com>,
        devicetree <devicetree@...r.kernel.org>,
        Albert Ou <aou@...s.berkeley.edu>,
        Tobias Klauser <tklauser@...tanz.ch>,
        Robin Murphy <robin.murphy@....com>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        iommu@...ts.linux-foundation.org,
        Guo Ren <guoren@...ux.alibaba.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Frank Rowand <frowand.list@...il.com>,
        Dmitry Vyukov <dvyukov@...gle.com>
Subject: Re: [RFC 3/5] dma-mapping: Enable global non-coherent pool support
 for RISC-V

On Mon, Jul 26, 2021 at 12:00 AM Christoph Hellwig <hch@....de> wrote:
>
> On Fri, Jul 23, 2021 at 02:40:29PM -0700, Atish Patra wrote:
> > Currently, linux,dma-default is used to reserve a global non-coherent pool
> > to allocate memory for dma operations. This can be useful for RISC-V as
> > well as the ISA specification doesn't specify a method to modify PMA
> > attributes or page table entries to define non-cacheable area yet.
> > A non-cacheable memory window is an alternate options for vendors to
> > support non-coherent devices.
>
> Please explain why you do not want to use the simply non-cachable
> window support using arch_dma_set_uncached as used by mips, niops2 and
> xtensa.
>

arch_dma_set_uncached works as well in this case. However, mips,
niops2 & xtensa uses a
fixed (via config) value for the offset. Similar approach can't be
used here because the platform specific
offset value has to be determined at runtime so that a single kernel
image can boot on all platforms.
That's why we need the following additional changes for RISC-V to make it work.

1. a new DT property so that arch specific code is aware of the
non-cacheable window offset.
    - either under /chosen node or a completely separate node with
multiple non-cacheable window support
   We also need to define how it is going to referenced from
individual device if a per-device non-cacheable
   window support is required in future. As of now, the beagleV memory
region lies in 0x10_0000_00000 - x17_FFFF_FFFF
   which is mapped to start of DRAM 0x80000000. All of the
non-coherent devices can do 32bit DMA only.

2. Use the dma-ranges and modify the arch_dma_set_uncached function to
pass the struct device as an argument.

Either way, we will need arch specific hook ups and additional changes
while the global non-coherent pool
provides a more elegant solution without any additional arch specific code.

If arch_dma_set_uncached is still preferred way to solve this problem,
I can revise the patch with either approach 1 or approach 2

> > +static int __dma_init_global_coherent(phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
>
>
>
>
> >  {
> >       struct dma_coherent_mem *mem;
> >
> > -     mem = dma_init_coherent_memory(phys_addr, phys_addr, size, true);
> > +     if (phys_addr == device_addr)
> > +             mem = dma_init_coherent_memory(phys_addr, device_addr, size, true);
> > +     else
> > +             mem = dma_init_coherent_memory(phys_addr, device_addr, size, false);
>
> Nak.  The phys_addr != device_addr support is goign away.  This needs

ok.

> to be filled in using dma-ranges property hanging of the struct device.

struct device is only accessible in rmem_dma_device_init. I couldn't
find a proper way to access it during
dma_reserved_default_memory setup under global pool.

Does that mean we should use a per-device memory pool instead of a
global non-coherent pool ?

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-- 
Regards,
Atish

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