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Message-Id: <20210726153833.031465366@linuxfoundation.org>
Date: Mon, 26 Jul 2021 17:37:52 +0200
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org,
Fabrice Gasnier <fabrice.gasnier@...s.st.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Sasha Levin <sashal@...nel.org>
Subject: [PATCH 4.19 020/120] ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings
From: Alexandre Torgue <alexandre.torgue@...s.st.com>
[ Upstream commit 2388f14d8747f8304e26ee870790e188c9431efd ]
Prevent warning seen with "make dtbs_check W=1" command:
Warning (avoid_unnecessary_addr_size): /soc/timers@...01c00: unnecessary
address-cells/size-cells without "ranges" or child "reg" property
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/arm/boot/dts/stm32f429.dtsi | 8 --------
arch/arm/boot/dts/stm32f746.dtsi | 8 --------
arch/arm/boot/dts/stm32h743.dtsi | 4 ----
3 files changed, 20 deletions(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b16bf00977d5..fdaf43290006 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -263,8 +263,6 @@
};
timers13: timers@...01c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@@ -278,8 +276,6 @@
};
timers14: timers@...02000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@@ -558,8 +554,6 @@
};
timers10: timers@...14400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@@ -573,8 +567,6 @@
};
timers11: timers@...14800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f48d06a80d1d..ccd87e833049 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -258,8 +258,6 @@
};
timers13: timers@...01c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@@ -273,8 +271,6 @@
};
timers14: timers@...02000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@@ -521,8 +517,6 @@
};
timers10: timers@...14400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@@ -536,8 +530,6 @@
};
timers11: timers@...14800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 637beffe5067..729ff6264776 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -422,8 +422,6 @@
};
lptimer4: timer@...02c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
@@ -438,8 +436,6 @@
};
lptimer5: timer@...03000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
--
2.30.2
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