linux-kernel - Re: [PATCH v2 2/2] clk: qcom: Add Global Clock controller (GCC) driver for SM6115

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Date:   Tue, 27 Jul 2021 11:33:46 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Iskren Chernev <iskren.chernev@...il.com>
Cc:     Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, phone-devel@...r.kernel.org,
        ~postmarketos/upstreaming@...ts.sr.ht,
        Iskren Chernev <iskren.chernev@...il.com>
Subject: Re: [PATCH v2 2/2] clk: qcom: Add Global Clock controller (GCC) driver for SM6115

Quoting Iskren Chernev (2021-06-27 11:55:38)
> diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
> new file mode 100644
> index 000000000000..e3c830b33dec
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sm6115.c
> @@ -0,0 +1,3623 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>

Should be clk-provider.h in this list as well.

> +
> +#include <dt-bindings/clock/qcom,gcc-sm6115.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> +       P_BI_TCXO,
> +       P_CORE_BI_PLL_TEST_SE,
> +       P_GPLL0_OUT_AUX2,
> +       P_GPLL0_OUT_EARLY,
> +       P_GPLL10_OUT_MAIN,
> +       P_GPLL11_OUT_AUX,
> +       P_GPLL11_OUT_AUX2,
> +       P_GPLL11_OUT_MAIN,
> +       P_GPLL3_OUT_EARLY,
> +       P_GPLL3_OUT_MAIN,
> +       P_GPLL4_OUT_MAIN,
> +       P_GPLL6_OUT_EARLY,
> +       P_GPLL6_OUT_MAIN,
> +       P_GPLL7_OUT_MAIN,
> +       P_GPLL8_OUT_EARLY,
> +       P_GPLL8_OUT_MAIN,
> +       P_GPLL9_OUT_EARLY,
> +       P_GPLL9_OUT_MAIN,
> +       P_SLEEP_CLK,
> +};
> +
> +static const struct parent_map gcc_parent_map_0[] = {
> +       { P_BI_TCXO, 0 },
> +       { P_GPLL0_OUT_EARLY, 1 },
> +       { P_GPLL0_OUT_AUX2, 2 },
> +       { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const char * const gcc_parent_names_0[] = {

Please use struct clk_parent_data instead of these arrays of strings.

> +       "bi_tcxo",
> +       "gpll0",
> +       "gpll0_out_aux2",
> +       "core_bi_pll_test_se",
> +};

And add newlines between structs.

> +static const char * const gcc_parent_names_0_ao[] = {
> +       "bi_tcxo_ao",
> +       "gpll0",
> +       "gpll0_out_aux2",
> +       "core_bi_pll_test_se",
> +};
> +